公开(公告)号：US11309392B2

公开(公告)日：2022-04-19

申请号：US16863253

申请日：2020-04-30

Applicant: BOE Technology Group Co., Ltd.

Inventor： Chunping Long ,  Hui Li

IPC: G09G3/30 ,  H01L29/417 ,  H01L27/12 ,  H01L29/786 ,  H01L29/66 ,  G09G3/3266 ,  H01L27/32

Abstract: The present disclosure provides a thin film transistor, a display panel and a method for manufacturing the thin film transistor. The thin film transistor includes an active layer and a source-drain electrode layer, the source-drain electrode layer includes a first electrode having at least one first electrode strip and a second electrode having at least one second electrode strip, the at least one first electrode strip and the at least one second electrode strip are alternately arranged at intervals, and at least an insulating part of a layer where the active layer is located is provided with an insulating material, and the insulating part is located at an orthographic projection of at least a part of a region between a free end of the first electrode strip, which is proximal to the second electrode, and the second electrode, on the layer where the active layer is located.

公开(公告)号：US11264509B2

公开(公告)日：2022-03-01

申请号：US16642820

申请日：2019-05-31

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Chunping Long

IPC: H01L29/786 ,  H01L27/12

Abstract: A thin film transistor, an array substrate, a display panel and a display device are provided, which is related to the field of display technologies. A thin film transistor comprises: a substrate; at least two active layers on the substrate, each active layer comprising a first terminal and a second terminal opposite to each other; a source and a drain above the substrate. The first terminal of each of the at least two active layers is electrically connected to the source, and the second terminal of each of the at least two active layers is electrically connected to the drain, and the at least two active layers are arranged on an upper surface of the substrate and separated from one another.

公开(公告)号：US11251223B2

公开(公告)日：2022-02-15

申请号：US16335453

申请日：2018-11-29

Applicant: BOE Technology Group Co., Ltd.

Inventor： Chunping Long

IPC: H01L27/14 ,  H01L27/15 ,  H01L27/12 ,  H01L33/00 ,  H01L33/12 ,  H01L33/38 ,  H01L33/62

Abstract: An array substrate includes a base substrate, a thin film transistor on the base substrate, including a gate electrode connected to a gate line, an active layer, a gate insulating layer insulating the gate electrode from the active layer, a first electrode connected to a data line, and a second electrode spaced apart from the first electrode, and a micro light emitting diode on the base substrate, including a first electrode, a first buffer layer, a light emitting layer, and a second electrode, which are stacked on top of each other. The first buffer layer is in a same layer as the active layer. The second electrode of the thin film transistor is connected to one of the first electrode of the micro light emitting diode or the second electrode of the micro light emitting diode.

公开(公告)号：US11175549B2

公开(公告)日：2021-11-16

申请号：US16326474

申请日：2018-05-22

Applicant: BOE Technology Group Co., Ltd.

Inventor： Chunping Long ,  Yongda Ma ,  Jian Xu

IPC: G02F1/1368 ,  G02F1/1362 ,  H01L27/12

Abstract: Disclosed are a display substrate, a display panel, a display device. The display substrate includes pixel units on a substrate in form of array, gate lines in one-to-one correspondence to each row of pixel units, data lines between any two adjacent columns of pixel units and on sides, far away from the substrate, of gate lines, each pixel unit includes a pixel electrode, a thin film transistor configured to control the pixel electrode; each data line includes curved data line parts between any two pixel units, whose row directions are adjacent to each other, in two columns of pixel units on two sides of data line; each data line part includes a first part covered by a pixel electrode of pixel unit on one side of the data line part, a second part covered by a pixel electrode of pixel unit on the other side of the data line part.

公开(公告)号：US11151913B2

公开(公告)日：2021-10-19

申请号：US16754953

申请日：2019-09-09

Applicant: BOE Technology Group Co., Ltd.

Inventor： Chunping Long

IPC: G09G3/00 ,  G09G3/20

Abstract: Some embodiments of the present disclosure provide an array substrate, a display panel and a display device. The array substrate includes a test circuit located in a non-display area, wherein the test circuit includes at least one stage of subcircuit, and the subcircuit includes at least one demux; except the first stage of subcircuit, the input ends of the demuxes in the subcircuit are connected with corresponding output ends of the demuxes in the previous stage of subcircuit; except the last stage of subcircuit, the output ends of the demuxes in the subcircuit are connected with corresponding input ends of the demuxes in the next stage of subcircuit; and the input end of the demux in the first stage of subcircuit is connected with a test terminal, and the output ends of the demuxes in the last stage of subcircuit are connected with signal lines in a display area.

公开(公告)号：US20210082963A1

公开(公告)日：2021-03-18

申请号：US16633184

申请日：2019-06-26

Applicant: BOE Technology Group Co., Ltd.

Inventor： Chunping Long

IPC: H01L27/12 ,  H01L27/02 ,  G09G3/20

Abstract: An electrostatic protection circuit and a manufacturing method thereof, an array substrate and a display apparatus in the field of display technology are provided. This electrostatic protection circuit includes: a discharge sub-circuit, a buffer sub-circuit and an electrostatic protection line, wherein the electrostatic protection line is a common electrode line; the buffer sub-circuit includes a third transistor and a fourth transistor; a gate and a second electrode of the third transistor are both connected to a first electrode of the fourth transistor, and the first electrode of the third transistor is connected to a signal line; a gate and a second electrode of the fourth transistor are both connected to the signal line.

公开(公告)号：US10446410B2

公开(公告)日：2019-10-15

申请号：US15321537

申请日：2016-03-07

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Xiaoyong Lu ,  Chunping Long ,  Chien Hung Liu ,  Yucheng Chan ,  Xiaolong Li ,  Zheng Liu

IPC: H01L21/321 ,  H01L21/306 ,  H01L21/768 ,  H01L21/3105 ,  H01L21/3213 ,  H01L21/02 ,  H01L21/48

Abstract: Embodiments of the present invention provide a method of processing a surface of a polysilicon and a method of processing a surface of a substrate assembly. The method of processing a surface of a polysilicon includes forming a material film on the surface of the polysilicon; and processing, by using a chemico-mechanical polishing technology, the surface of the polysilicon on which the material film is formed. The material film is selected such that the polysilicon is preferentially removed in a polishing process.

公开(公告)号：US20180252969A1

公开(公告)日：2018-09-06

申请号：US15791376

申请日：2017-10-23

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Chunping Long ,  Yongda Ma

IPC: G02F1/1343 ,  G02F1/1337 ,  G02F1/1362 ,  H01L27/12 ,  H01L27/32 ,  H01L29/417

CPC classification number: G02F1/134309 ,  G02F1/1337 ,  G02F1/136209 ,  G02F1/136286 ,  G02F2001/13606 ,  H01L27/1262 ,  H01L27/3244 ,  H01L27/3248 ,  H01L29/41733 ,  H01L2021/775

Abstract: The present disclosure provides an array substrate and a display device. The array substrate includes: first common electrode lines; gate lines; a gate insulation layer; data lines, the first common electrode lines crossing the data lines to define a plurality of pixel units, each gate line dividing a corresponding pixel unit into two sub-regions, a separate TFT being arranged at each sub-region; second common electrode lines; and a drain electrode pad arranged at each sub-region and a drain electrode connection line for connecting the drain electrode pad to a drain electrode of the TFT. The drain electrode pad, the drain electrode connection line and the drain electrode are arranged at an identical layer. An orthogonal projection of each second common electrode line onto the base substrate overlaps an orthogonal projection of the drain electrode pad onto the base substrate.

公开(公告)号：US20180203311A1

公开(公告)日：2018-07-19

申请号：US15566610

申请日：2017-03-30

Applicant: BOE Technology Group Co., Ltd.

Inventor： Chunping Long ,  Jianbo Xian

IPC: G02F1/1362 ,  G02F1/1345 ,  G09G3/00 ,  G09G3/36 ,  H01L27/12 ,  H01L27/02 ,  H01L29/49 ,  H01L29/786

CPC classification number: G02F1/136204 ,  G02F1/13454 ,  G02F2001/136254 ,  G09G3/006 ,  G09G3/36 ,  G09G2300/0426 ,  G09G2330/04 ,  G09G2330/06 ,  H01L27/0251 ,  H01L27/0266 ,  H01L27/1214 ,  H01L27/1248 ,  H01L29/4908 ,  H01L29/78675

Abstract: An array substrate circuit including an electrostatic discharge circuit for supplying electrostatic discharge to a first signal line for supplying a test signal to the first signal line; wherein, the electrostatic discharge circuit and the test circuit have a shared portion. The array substrate circuit can achieve a lower load of a signal line, and is conducive to achieving a narrow frame panel. An array substrate including the array substrate circuit and a display device are further disclosed.

公开(公告)号：US20180190645A1

公开(公告)日：2018-07-05

申请号：US15562853

申请日：2017-03-14

Applicant: BOE Technology Group Co., Ltd.

Inventor： Chunping Long ,  Jianbo Xian

IPC: H01L27/02 ,  H01L27/12

CPC classification number: H01L27/0266 ,  G02F1/1345 ,  G09G3/3648 ,  G09G2300/0809 ,  G09G2320/0209 ,  G09G2330/04 ,  H01L27/1251 ,  H01L27/3262 ,  H02H9/00

Abstract: An electrostatic discharge (ESD) circuit, an array substrate and a display device are provided. The ESD circuit including a first signal line, a second signal line and a first thin film transistor, wherein the first TFT includes a plurality of first sub-TFTs; each first sub-TFT includes a first source electrode and a first drain electrode; the first sub-TFTs are sequentially arranged; adjacent first sub-TFTs share one first source electrode or first drain electrode; one of the first signal line and the second signal line is electrically connected with the first drain electrode of each first sub-TFT; and the other is electrically connected with the first source electrode of each first sub-TFT.