公开(公告)号：US12230340B2

公开(公告)日：2025-02-18

申请号：US17996293

申请日：2021-11-30

Applicant: BOE Technology Group Co., Ltd.

Inventor： Yunsik Im ,  Shunhang Zhang ,  Fuqiang Li ,  Changfeng Li ,  Liwei Liu ,  Hehe Hu ,  Ce Ning ,  Hui Zhang ,  Hongrun Wang ,  Zhuo Li

IPC: G11C19/28 ,  G09G3/20 ,  G09G3/3266 ,  G09G3/36

Abstract: The present disclosure provides a shift register unit, a gate driving circuit and a display device. The shift register unit provided by the present disclosure includes: an input sub-circuit, an output sub-circuit, at least one pull-down control sub-circuit, at least one pull-down sub-circuit, at least one first noise reduction sub-circuit, and a reverse bias sub-circuit; the reverse bias sub-circuit is configured to control transistors in at least part of sub-circuits connected to a pull-up node to be in a reverse bias state through a power voltage signal in response to a potential of the pull-up node, or control the transistors in at least part of the sub-circuits connected to the pull-up node to be in the reverse bias state through a cascade signal in response to a potential of a cascade signal terminal.

公开(公告)号：US12183298B2

公开(公告)日：2024-12-31

申请号：US17788113

申请日：2021-08-27

Applicant: BOE Technology Group Co., Ltd.

Inventor： Hui Zhang ,  Kai Hou ,  Hongrun Wang ,  Shunhang Zhang ,  Liwei Liu ,  Yunsik Im ,  Changfeng Li ,  Fuqiang Li

IPC: G02F1/1362 ,  G02F1/1368 ,  G09G3/36 ,  G09G3/32

Abstract: Disclosed are a display panel, a display apparatus, a driving method thereof. The display panel includes: a first base substrate; scanning lines; data lines; sub-pixels, in regions divided by the scanning lines and the data lines, at least two sub-pixels adjacent in a first direction and a second direction constitute a pixel island, the sub-pixels constitute pixel islands, each pixel island includes n sub-pixel rows in the second direction; scanning signal input lines, in one-to-one correspondence to the scanning lines; control signal lines; fixed potential lines; and control circuits, located between the adjacent sub-pixels. One pixel island is connected to at least n control circuits, one control circuit corresponds to one row of sub-pixels in the pixel island. The control circuits are configured to: transfer, under control of control signal lines, signals provided by the scanning signal input lines or the fixed potential lines to the scanning lines.

公开(公告)号：US12105372B2

公开(公告)日：2024-10-01

申请号：US18374109

申请日：2023-09-28

Applicant: BOE Technology Group Co., Ltd.

Inventor： Ge Shi ,  Yujie Liu ,  Shi Shu ,  Wei Huang ,  Shiyu Zhang ,  Yuyao Wang ,  Yunsik Im ,  Xiaochuan Chen ,  Xue Dong ,  Ming Zhu ,  Song Yang

IPC: G02F1/1335

CPC classification number: G02F1/133514 ,  G02F1/133512 ,  G02F1/133548

Abstract: A color filter substrate, a display panel and a display device are provided. The color filter substrate includes: a base substrate; a color conversion layer on the base substrate; a covering layer on a side of the color conversion layer away from the base substrate; and a polarizing layer on a side of the covering layer away from the base substrate. The polarizing layer includes a wire grid polarizer. The covering layer includes a first covering sub-layer and a second covering sub-layer, the first covering sub-layer is located on the side of the color conversion layer away from the base substrate, the second covering sub-layer is located on a side of the first covering sub-layer away from the base substrate, and a material of the first covering sub-layer is different from a material of the second covering sub-layer.

公开(公告)号：US11435634B2

公开(公告)日：2022-09-06

申请号：US17263305

申请日：2020-03-31

Applicant: BOE Technology Group Co., Ltd.

Inventor： Liwei Liu ,  Yunsik Im ,  Shunhang Zhang ,  Kai Hou ,  Hui Zhang ,  Hongrun Wang

IPC: G02F1/1362 ,  G02F1/1339

Abstract: A display panel and a display device are provided. The display panel includes a first substrate and a second substrate. The first substrate includes: a first base substrate; and a plurality of spacers on the first base substrate, including a first sub spacer and a second sub spacer; and the second substrate includes: a second base substrate; a gate line; a plurality of sub-pixels on the second base substrate; a first boss and a second boss on the second base substrate. The second substrate includes a first row of pixels and a second row of pixels adjacent to the first row of pixels; an orthographic projection of the second boss and an orthographic projection of the gate line on the second base substrate overlap; an orthographic projection of the first sub spacer and an orthographic projection of the first boss on the second base substrate at least partially overlap.

公开(公告)号：US20210356831A1

公开(公告)日：2021-11-18

申请号：US17263305

申请日：2020-03-31

Applicant: BOE Technology Group Co., Ltd.

Inventor： Liwei Liu ,  Yunsik Im ,  Shunhang Zhang ,  Kai Hou ,  Hui Zhang ,  Hongrun Wang

IPC: G02F1/1362

Abstract: A display panel and a display device are provided. The display panel includes a first substrate and a second substrate. The first substrate includes: a first base substrate; and a plurality of spacers on the first base substrate, including a first sub spacer and a second sub spacer; and the second substrate includes: a second base substrate; a gate line; a plurality of sub-pixels on the second base substrate; a first boss and a second boss on the second base substrate. The second substrate includes a first row of pixels and a second row of pixels adjacent to the first row of pixels; an orthographic projection of the second boss and an orthographic projection of the gate line on the second base substrate overlap; an orthographic projection of the first sub spacer and an orthographic projection of the first boss on the second base substrate at least partially overlap.

公开(公告)号：US10747077B2

公开(公告)日：2020-08-18

申请号：US16108956

申请日：2018-08-22

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Feng Liao ,  Xue Dong ,  Jing Lv ,  Yunsik Im ,  Yoonsung Um ,  Xinxing Wang

IPC: G09G3/36 ,  G02F1/1362 ,  G02F1/1335 ,  H01L27/12 ,  G06F3/047

Abstract: The present disclosure provides a display substrate and a display device. The display substrate includes a base substrate, a plurality of data lines and a plurality of pixels arranged in an array on the base substrate, each of the data lines extends along a column direction, the pixels in a single column are connected to one single data line of the data lines, any two data lines of the data lines connected to adjacent columns of the pixels constitute a pair of data lines, any two adjacent pixels in each row of the pixels constitute a pair of pixels, each pair of data lines pass through one row of any two adjacent rows of the pixels by extending between two pairs of pixels, and pass through another one row of the two adjacent rows of the pixels by extending between two pixels of one pair of pixels.

公开(公告)号：US10578945B2

公开(公告)日：2020-03-03

申请号：US16026444

申请日：2018-07-03

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Zheng Fang ,  Yunsik Im

IPC: G02F1/29

Abstract: The present disclosure relates to a liquid crystal lens assembly, a liquid crystal panel, and a liquid crystal display device. The liquid crystal lens assembly includes: a liquid crystal layer, a first electrode layer having a plurality of first bar electrodes, and a second electrode layer having a plurality of second bar electrodes. The first electrode layer and the second electrode layer are both provided on a first side of the liquid crystal layer, and an extending direction of the first bar electrodes intersects with an extending direction of the second bar electrodes. The present disclosure can increase a utilization efficiency of light beams, and reduce a power consumption of the light source side.

公开(公告)号：US10416508B2

公开(公告)日：2019-09-17

申请号：US15564938

申请日：2017-05-15

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Hui Li ,  Yunsik Im ,  Hyunsic Choi ,  Liwei Liu

IPC: G02F1/1343 ,  G02F1/1337 ,  H01L21/84 ,  H01L27/12 ,  G02F1/136 ,  G02F1/1362

Abstract: Array substrate, display panel, and display device, and their fabrication methods are provided. An array substrate includes a plurality of subpixels, each including a first electrode and a second electrode, electrically isolated from one another, on a substrate. The first electrode includes a plurality of electrically connected first electrode strips. The second electrode includes a plurality electrically connected second electrode strips alternately arranged with the first electrode strips. A first distance along a first direction at any position between one first electrode strip and a first neighboring second electrode strip is substantially same. Along a length direction of the first electrode strips, a first width of each first electrode strip has a varying value at a different position.

公开(公告)号：US20180307080A1

公开(公告)日：2018-10-25

申请号：US15564938

申请日：2017-05-15

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Hui Li ,  Yunsik Im ,  Hyunsic Choi ,  Liwei Liu

IPC: G02F1/1343 ,  G02F1/1337 ,  H01L21/84 ,  H01L27/12 ,  G02F1/136

CPC classification number: G02F1/13439 ,  G02F1/133707 ,  G02F1/1343 ,  G02F1/134309 ,  G02F1/136 ,  G02F1/1362 ,  G02F2201/122 ,  G02F2201/123 ,  H01L21/84 ,  H01L27/12 ,  H01L27/124 ,  H01L27/1296

Abstract: Array substrate, display panel, and display device, and their fabrication methods are provided. An array substrate includes a plurality of subpixels, each including a first electrode and a second electrode, electrically isolated from one another, on a substrate. The first electrode includes a plurality of electrically connected first electrode strips. The second electrode includes a plurality electrically connected second electrode strips alternately arranged with the first electrode strips. A first distance along a first direction at any position between one first electrode strip and a first neighboring second electrode strip is substantially same. Along a length direction of the first electrode strips, a first width of each first electrode strip has a varying value at a different position.

公开(公告)号：US20180108426A1

公开(公告)日：2018-04-19

申请号：US15504119

申请日：2016-08-12

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Haoliang Zheng ,  Seungwoo Han ,  Xing Yao ,  Hyunsic Choi ,  Guangliang Shang ,  Mingfu Han ,  Yunsik Im ,  Jungmok JUN ,  Xue Dong

IPC: G11C19/28 ,  G09G3/36 ,  H01L27/12 ,  G11C19/18

CPC classification number: G11C19/28 ,  G09G3/20 ,  G09G3/3677 ,  G09G3/3688 ,  G09G2310/0267 ,  G09G2310/0286 ,  G11C19/184 ,  H01L27/1222 ,  H01L27/124 ,  H01L27/1251

Abstract: The present application discloses a method of driving a gate driving circuit in an operation cycle divided into a first sub-cycle and a second sub-cycle, including providing a gate driving circuit having a first plurality of shift register units with a second plurality of shift register units, the first plurality of shift register units being configured so that each odd/even numbered shift register unit includes a first bias-control terminal to receive a first/second bias signal CLK1/CLK2, a second bias-control terminal to receive a second/first bias signal CLK2/CLK1, and a first control level terminal provided with a first control voltage VC1, the second plurality of shift register units being configured so that each odd/even numbered shift register unit includes a third bias-control terminal to receive a third/fourth bias signal CLK3/CLK4, a fourth bias-control terminal to receive a fourth/third bias signal CLK4/CLK3, and a second control level terminal provided with a second control voltage VC2; configuring the first bias signal CLK1 and the second bias signal CLK2 as first pair of clock signals at respective turn-on level and turn-off level with inverted phase in the first sub-cycle; setting the first control voltage VC1 to a turn-off level so that the first plurality of shift register units is controlled along with the first pair of clock signals to respectively output corresponding gate driving output signals in an output phase within the first sub-cycle; setting both the third bias signal CLK3 and the fourth bias signal CLK4 to a turn-off level and the second control voltage VC2 to turn-on level during the first sub-cycle; configuring the third bias signal CLK3 and the fourth bias signal CLK4 as second pair of clock signals at respective turn-on level and turn-off level with inverted phase in the second sub-cycle; setting the second control voltage VC2 to a turn-off level so that the second plurality of shift register units are controlled along with the second pair of clock signals to respectively output corresponding gate driving output signals in an output phase within the second sub-cycle; and setting the first bias signal CLK1 and the second bias signal CLK2 to a turn-off level and the second control voltage VC1 to a turn-on level during the second sub-cycle.