公开(公告)号：US20230178373A1

公开(公告)日：2023-06-08

申请号：US17541459

申请日：2021-12-03

Applicant: Applied Materials, Inc.

Inventor： Qintao Zhang ,  Samphy Hong ,  Wei Zou

IPC: H01L21/266 ,  H01L21/04 ,  H01L29/16

CPC classification number: H01L21/266 ,  H01L21/0465 ,  H01L29/1608

Abstract: Disclosed herein are methods for increasing MOSFET threshold voltage to enable higher SiC mobility. In some embodiments, a method includes providing a device structure including a dielectric layer over an epitaxial layer, patterning a hardmask layer over the dielectric layer, performing a first ion implant to form a well in the epitaxial layer, and performing a second ion implant to form an interface layer between the well and the dielectric layer.

公开(公告)号：US11527412B2

公开(公告)日：2022-12-13

申请号：US17113073

申请日：2020-12-06

Applicant: Applied Materials, Inc.

Inventor： Qintao Zhang ,  Samphy Hong ,  David J. Lee ,  Felix Levitov ,  Lei Zhong ,  Wei Zou

IPC: H01L21/311 ,  H01J37/317 ,  H01L21/3115

Abstract: A method for performing an ion implantation process including providing a hardmask layer disposed atop a substrate, providing a photoresist layer disposed atop the hardmask layer and defining a pattern exposing a portion of the hardmask layer, performing a room temperature ion implantation process wherein an ion beam formed of an ionized first dopant species is directed onto the exposed portion of the hardmask layer to make the exposed portion more susceptible to ion etching or wet etching, performing an etching process wherein the exposed portion of the hardmask layer is etched away to expose an underlying portion of the substrate, and performing a high energy, hot ion implantation process wherein an ion beam formed of a ionized second dopant species is directed onto the exposed portion of the substrate.

公开(公告)号：US20220344453A1

公开(公告)日：2022-10-27

申请号：US17238504

申请日：2021-04-23

Applicant: Applied Materials, Inc.

Inventor： Qintao Zhang ,  Samphy Hong ,  Jason Appell ,  David J. Lee

IPC: H01L29/06 ,  H01L29/16 ,  H01L29/10 ,  H01L29/78 ,  H01L21/04 ,  H01L21/76 ,  H01L21/761 ,  H01L29/66

Abstract: Methods may include providing a device structure including a well formed in an epitaxial layer, and forming a plurality of shielding layers in the device structure, wherein at least one shielding layer is formed between a pair of adjacent sacrificial gates of a plurality of sacrificial gates. The method may further include forming a contact over the at least one shielding layer, forming a fill layer over the contact, and forming a plurality of trenches into the device structure, wherein at least one trench of the plurality of trenches is formed between a pair of adjacent shielding layers of the plurality of shielding layers, and wherein the at least one trench of the plurality of trenches is defined in part by a sidewall of the fill layer. The method may further include forming a gate structure within the at least one trench of the plurality of trenches.

公开(公告)号：US20220199806A1

公开(公告)日：2022-06-23

申请号：US17127298

申请日：2020-12-18

Applicant: Applied Materials, Inc.

Inventor： Qintao Zhang ,  Samphy Hong ,  Wei Zou ,  Lei Zhong ,  David J. Lee ,  Felix Levitov

IPC: H01L29/66 ,  H01L21/28

Abstract: Disclosed herein are methods for forming MOSFETs. In some embodiments, a method may include providing a device structure including a plurality of trenches, and forming a mask over the device structure including within each of the plurality of trenches and over a top surface of the device structure. The method may further include removing the mask from within the trenches, wherein the mask remains along the top surface of the device structure, and implanting the device structure to form a treated layer along a bottom of the trenches. In some embodiments, the method may further include forming a gate oxide layer along a sidewall of each of the trenches and along the bottom of the trenches, wherein a thickness of the oxide along the bottom of the trenches is greater than a thickness of the oxide along the sidewall of each of the trenches.