公开(公告)号：US20170084214A1

公开(公告)日：2017-03-23

申请号：US15162974

申请日：2016-05-24

Applicant: Apple Inc.

Inventor： Shinya Ono ,  Chun-Yao Huang ,  Hao-Lin Chiu ,  Ivan Knez ,  Patrick B. Bennett ,  Shih Chang Chang ,  Byung Duk Yang

IPC: G09G3/20 ,  H01L27/12

CPC classification number: G09G3/20 ,  G02F1/136286 ,  G02F2001/13456 ,  G09G2300/0413 ,  G09G2300/0426 ,  G09G2300/043 ,  G09G2300/08 ,  G09G2310/0278 ,  G09G2310/0281 ,  G09G2320/0209 ,  G09G2320/0219 ,  H01L27/124

Abstract: A display may have an array of pixels arranged in rows and columns. Display driver circuitry may be provided along an edge of the display. Data lines that are associated with columns of the pixels may be used to distribute data from the display driver circuitry to the pixels. Gate lines in the display may each have a horizontal straight portion that extends along a respective row of the pixels and may each have one or more non-horizontal segments such as zigzag segments. The non-horizontal portion of each gate line may be connected to the horizontal straight portion of the gate line by a via. The non-horizontal portions may each have portions that are overlapped by portions of the data lines. Dummy gate line structures may be provided on the display that are not coupled to any of the pixels in the display.

公开(公告)号：US11651736B2

公开(公告)日：2023-05-16

申请号：US17680059

申请日：2022-02-24

Applicant: Apple Inc.

Inventor： Chin-Wei Lin ,  Shinya Ono ,  Zino Lee ,  Yun Wang ,  Fan Gui

IPC: G09G3/3258 ,  H01L27/32 ,  H01L29/786

CPC classification number: G09G3/3258 ,  H01L27/3262 ,  H01L29/7869 ,  G09G2300/0842 ,  G09G2320/0233 ,  G09G2320/043

Abstract: A display pixel is provided that is operable to support hybrid compensation scheme having both in-pixel threshold voltage canceling and external threshold voltage compensation. The display may include multiple p-type silicon transistors with at least one n-type semiconducting-oxide transistor and one storage capacitor. An on-bias stress phase may be performed prior to a threshold voltage sampling and data programming phase to mitigate hysteresis and improve first frame response. In low refresh rate displays, a first additional on-bias stress operation can be performed separate from the threshold voltage sampling and data programming phase during a refresh frame and a second additional on-bias stress operation can be performed during a vertical blanking frame. The display pixel may be configured to receive an initialization voltage and an anode reset voltage, either of which can be dynamically tuned to match the stress of the first and second additional on-bias stress operations to minimize flicker.

公开(公告)号：US11615746B2

公开(公告)日：2023-03-28

申请号：US17884297

申请日：2022-08-09

Applicant: Apple Inc.

Inventor： Chin-Wei Lin ,  Hung Sheng Lin ,  Shih Chang Chang ,  Shinya Ono

IPC: G09G3/3233 ,  G09G3/3266 ,  H01L29/786 ,  G09G3/3275 ,  H01L27/12

Abstract: A display may have an array of pixels each of which has a light-emitting diode such as an organic light-emitting diode. A drive transistor and an emission transistor may be coupled in series with the light-emitting diode of each pixel between a positive power supply and a ground power supply. The pixels may include first and second switching transistors. A data storage capacitor may be coupled between a gate and source of the drive transistor in each pixel. Signal lines may be provided in columns of pixels to route signals such as data signals, sensed drive currents from the drive transistors, and predetermined voltages between display driver circuitry and the pixels. The switching transistors, emission transistors, and drive transistors may include semiconducting-oxide transistors and silicon transistors and may be n-channel transistors or p-channel transistors.

公开(公告)号：US11580905B2

公开(公告)日：2023-02-14

申请号：US17749045

申请日：2022-05-19

Applicant: Apple Inc.

Inventor： Rungrot Kitsomboonloha ,  Chin-Wei Lin ,  Shinya Ono ,  Gihoon Choo ,  Hao-Lin Chiu ,  Kyung Wook Kim ,  Pei-En Chang ,  Szu-Hsien Lee ,  Zino Lee

IPC: G09G3/3225

Abstract: A display may include an array of pixels that receive control signals from a chain of gate drivers. Each gate driver may include a logic sub-circuit and an output buffer sub-circuit. The output buffer sub-circuit may include depletion mode semiconducting oxide transistors with high mobility. The logic sub-circuit may include semiconducting oxide transistors, some of which can be depletion mode transistors and some of which can be enhancement mode transistors with lower mobility. The logic sub-circuit may include at least a carry circuit, a voltage setting circuit, an inverting circuit, a discharge circuit.

公开(公告)号：US11532282B2

公开(公告)日：2022-12-20

申请号：US17501530

申请日：2021-10-14

Applicant: Apple Inc.

Inventor： Shinya Ono ,  Chin-Wei Lin ,  Zino Lee ,  Chun-Chieh Lin ,  Chen-Ming Chen

IPC: G09G3/3291 ,  G09G3/3266

Abstract: A display may include an array of pixels. Each pixel in the array includes an organic light-emitting diode coupled to a drive transistor, a data loading transistor, a first capacitor for storing data charge, and a second capacitor. During a data programming phase, the data loading transistor may be activated to load in a data value onto the first capacitor. After the data programming phase, the second capacitor may be configured to receive a lower voltage, which extends a threshold voltage sampling time for the pixel. Configured and operated in this way, the temperature luminance sensitivity of the display can be reduced.

公开(公告)号：US20220181418A1

公开(公告)日：2022-06-09

申请号：US17504230

申请日：2021-10-18

Applicant: Apple Inc.

Inventor： Jung Yen Huang ,  Shinya Ono ,  Chin-Wei Lin ,  Akira Matsudaira ,  Cheng Min Hu ,  Chih Pang Chang ,  Ching-Sang Chuang ,  Gihoon Choo ,  Jiun-Jye Chang ,  Po-Chun Yeh ,  Shih Chang Chang ,  Yu-Wen Liu ,  Zino Lee

IPC: H01L27/32 ,  H01L29/786 ,  H01L29/66

Abstract: A display may include an array of pixels. Each pixel in the array includes an organic light-emitting diode coupled to associated semiconducting oxide transistors. The semiconducting oxide transistors may exhibit different device characteristics. Some of the semiconducting oxide transistors may be formed using a first oxide layer formed from a first semiconducting oxide material using first processing steps, whereas other semiconducting oxide transistors are formed using a second oxide layer formed from a second semiconducting oxide material using second processing steps different than the first processing steps. The display may include three or more different semiconducting oxide layers formed during different processing steps.

公开(公告)号：US11232748B2

公开(公告)日：2022-01-25

申请号：US17222844

申请日：2021-04-05

Applicant: Apple Inc.

Inventor： Chin-Wei Lin ,  Hung Sheng Lin ,  Shih Chang Chang ,  Shinya Ono

IPC: G09G3/3233 ,  H01L29/786 ,  G09G3/3266 ,  G09G3/3275 ,  H01L27/12

Abstract: A display may have an array of pixels each of which has a light-emitting diode such as an organic light-emitting diode. A drive transistor and an emission transistor may be coupled in series with the light-emitting diode of each pixel between a positive power supply and a ground power supply. The pixels may include first and second switching transistors. A data storage capacitor may be coupled between a gate and source of the drive transistor in each pixel. Signal lines may be provided in columns of pixels to route signals such as data signals, sensed drive currents from the drive transistors, and predetermined voltages between display driver circuitry and the pixels. The switching transistors, emission transistors, and drive transistors may include semiconducting-oxide transistors and silicon transistors and may be n-channel transistors or p-channel transistors.

公开(公告)号：US20210305353A1

公开(公告)日：2021-09-30

申请号：US17143939

申请日：2021-01-07

Applicant: Apple Inc.

Inventor： Shinya Ono ,  Chin-Wei Lin ,  Akira Matsudaira ,  Jiun-Jye Chang ,  Jung Yen Huang ,  Pei-En Chang ,  Rungrot Kitsomboonloha ,  Szu-Hsien Lee

IPC: H01L27/32 ,  G09G3/3266 ,  G09G3/3225

Abstract: An electronic device may include a display with pixels formed using light-emitting diodes, thin-film silicon transistors, thin-film semiconducting-oxide transistors, and capacitors. The silicon transistors, semiconducting-transistors, and capacitors may have control terminals that are coupled to gate or routing lines that extend across the face of the display and that are formed in a low resistance source-drain metal routing layer. Forming routing/gate lines using the low resistance source-drain metal routing layer dramatically reduces the resistance of the gate lines, which enables better timing margins for large display panels operating at higher refresh rates.

公开(公告)号：US20210225283A1

公开(公告)日：2021-07-22

申请号：US17222844

申请日：2021-04-05

Applicant: Apple Inc.

Inventor： Chin-Wei Lin ,  Hung Sheng Lin ,  Shih Chang Chang ,  Shinya Ono

IPC: G09G3/3233 ,  H01L29/786 ,  G09G3/3266 ,  G09G3/3275 ,  H01L27/12

Abstract: A display may have an array of pixels each of which has a light-emitting diode such as an organic light-emitting diode. A drive transistor and an emission transistor may be coupled in series with the light-emitting diode of each pixel between a positive power supply and a ground power supply. The pixels may include first and second switching transistors. A data storage capacitor may be coupled between a gate and source of the drive transistor in each pixel. Signal lines may be provided in columns of pixels to route signals such as data signals, sensed drive currents from the drive transistors, and predetermined voltages between display driver circuitry and the pixels. The switching transistors, emission transistors, and drive transistors may include semiconducting-oxide transistors and silicon transistors and may be n-channel transistors or p-channel transistors.

公开(公告)号：US20210210022A1

公开(公告)日：2021-07-08

申请号：US17206425

申请日：2021-03-19

Applicant: Apple Inc.

Inventor： Ting-Kuo Chang ,  Abbas Jamshidi Roudbari ,  Tsung-Ting Tsai ,  Warren S. Rieutort-Louis ,  Shinya Ono ,  Shin-Hung Yeh ,  Chien-Ya Lee ,  Shyuan Yang

IPC: G09G3/3275 ,  G09G3/3233 ,  G09G3/3266

Abstract: A display may have rows and columns of pixels. Gate lines may be used to supply gate signals to rows of the pixels. Data lines may be used to supply data signals to columns of the pixels. The data lines may include alternating even and odd data lines. Data lines may be organized in pairs each of which includes one of the odd data lines and an adjacent one of the even data lines. Demultiplexer circuitry may be configured dynamically during data loading and pixel sensing operations. During data loading, data from display driver circuitry may be supplied, alternately to odd pairs of the data lines and even pairs of the data lines. During sensing, the demultiplexer circuitry may couple a pair of the even data lines to sensing circuitry in the display driver circuitry and then may couple a pair of the odd data lines to the sensing circuitry.