公开(公告)号：US11755333B2

公开(公告)日：2023-09-12

申请号：US17643765

申请日：2021-12-10

Applicant: Apple Inc.

Inventor： Brandon H. Dwiel ,  Andrew J. Beaumont-Smith ,  Eric J. Furbish ,  John D. Pape ,  Stephen G. Meier ,  Tyler J. Huberty

IPC: G06F9/38

CPC classification number: G06F9/3881 ,  G06F9/382 ,  G06F9/383 ,  G06F9/3877

Abstract: A prefetcher for a coprocessor is disclosed. An apparatus includes a processor and a coprocessor that are configured to execute processor and coprocessor instructions, respectively. The processor and coprocessor instructions appear together in code sequences fetched by the processor, with the coprocessor instructions being provided to the coprocessor by the processor. The apparatus further includes a coprocessor prefetcher configured to monitor a code sequence fetched by the processor and, in response to identifying a presence of coprocessor instructions in the code sequence, capture the memory addresses, generated by the processor, of operand data for coprocessor instructions. The coprocessor is further configured to issue, for a cache memory accessible to the coprocessor, prefetches for data associated with the memory addresses prior to execution of the coprocessor instructions by the coprocessor.

公开(公告)号：US11210104B1

公开(公告)日：2021-12-28

申请号：US17018963

申请日：2020-09-11

Applicant: Apple Inc.

Inventor： Aditya Kesiraju ,  Andrew J. Beaumont-Smith ,  Brian P. Lilly ,  James Vash ,  Jason M. Kassoff ,  Krishna C. Potnuru ,  Rajdeep L. Bhuyar ,  Ran A. Chachick ,  Tyler J. Huberty ,  Derek R. Kumar

IPC: G06F9/38 ,  G06F11/30 ,  G06F9/48 ,  G06F9/30

Abstract: A system may include a plurality of processors and a coprocessor. A plurality of coprocessor context priority registers corresponding to a plurality of contexts supported by the coprocessor may be included. The plurality of processors may use the plurality of contexts, and may program the coprocessor context priority register corresponding to a context with a value specifying a priority of the context relative to other contexts. An arbiter may arbitrate among instructions issued by the plurality of processors based on the priorities in the plurality of coprocessor context priority registers. In one embodiment, real-time threads may be assigned higher priorities than bulk processing tasks, improving bandwidth allocated to the real-time threads as compared to the bulk tasks.

公开(公告)号：US11176045B2

公开(公告)日：2021-11-16

申请号：US16832893

申请日：2020-03-27

Applicant: Apple Inc.

Inventor： Stephan G. Meier ,  Tyler J. Huberty ,  Nikhil Gupta

IPC: G06F12/00 ,  G06F12/0862 ,  G06F9/38

Abstract: In an embodiment, a processor includes a plurality of prefetch circuits configured to prefetch data into a data cache. A primary prefetch circuit may be configured to generate first prefetch requests in response to a demand access, and may be configured to invoke a second prefetch circuit in response to the demand access. The second prefetch circuit may implement a different prefetch mechanism than the first prefetch circuit. If the second prefetch circuit reaches a threshold confidence level in prefetching for the demand access, the second prefetch circuit may communicate an indication to the primary prefetch circuit. The primary prefetch circuit may reduce a number of prefetch requests generated for the demand access responsive to the communication from the second prefetch circuit.

公开(公告)号：US09886385B1

公开(公告)日：2018-02-06

申请号：US15247421

申请日：2016-08-25

Applicant: Apple Inc.

Inventor： Tyler J. Huberty ,  Stephan G. Meier ,  Mridul Agarwal

IPC: G06F12/08 ,  G06F12/0862 ,  G06F12/0897 ,  G06F12/0864

CPC classification number: G06F12/0862 ,  G06F12/0864 ,  G06F12/0897 ,  G06F2212/1024 ,  G06F2212/6022 ,  G06F2212/6024

Abstract: In a content-directed prefetcher, a pointer detection circuit identifies a given memory pointer candidate within a data cache line fill from a lower level cache (LLC), where the LLC is at a lower level of a memory hierarchy relative to the data cache. A pointer filter circuit initiates a prefetch request to the LLC candidate dependent on determining that a given counter in a quality factor (QF) table satisfies QF counter threshold value. The QF table is indexed dependent upon a program counter address and relative cache line offset of the candidate. Upon initiation of the prefetch request, the given counter is updated to reflect a prefetch cost. In response to determining that a subsequent data cache line fill arriving from the LLC corresponds to the prefetch request for the given memory pointer candidate, a particular counter of the QF table may be updated to reflect a successful prefetch credit.