公开(公告)号：US09940262B2

公开(公告)日：2018-04-10

申请号：US14491149

申请日：2014-09-19

Applicant: Apple Inc.

Inventor： Shyam Sundar ,  Richard F. Russo ,  Ronald P. Hall ,  Conrado Blasco

IPC: G06F12/1045 ,  G06F12/0875 ,  G06F9/38 ,  G06F9/32 ,  G06F12/1027

CPC classification number: G06F12/1045 ,  G06F9/324 ,  G06F9/3804 ,  G06F9/382 ,  G06F12/0875 ,  G06F12/1027 ,  G06F2212/452 ,  G06F2212/684

Abstract: A system and method for efficiently indicating branch target addresses. A semiconductor chip predecodes instructions of a computer program prior to installing the instructions in an instruction cache. In response to determining a particular instruction is a control flow instruction with a displacement relative to a program counter address (PC), the chip replaces a portion of the PC relative displacement in the particular instruction with a subset of a target address. The subset of the target address is an untranslated physical subset of the full target address. When the recoded particular instruction is fetched and decoded, the remaining portion of the PC relative displacement is added to a virtual portion of the PC used to fetch the particular instruction. The result is concatenated with the portion of the target address embedded in the fetched particular instruction to form a full target address.

公开(公告)号：US20160085550A1

公开(公告)日：2016-03-24

申请号：US14491149

申请日：2014-09-19

Applicant: Apple Inc.

Inventor： Shyam Sundar ,  Richard F. Russo ,  Ronald P. Hall ,  Conrado Blasco

IPC: G06F9/30 ,  G06F12/08 ,  G06F12/10 ,  G06F9/38

CPC classification number: G06F12/1045 ,  G06F9/324 ,  G06F9/3804 ,  G06F9/382 ,  G06F12/0875 ,  G06F12/1027 ,  G06F2212/452 ,  G06F2212/684

Abstract: A system and method for efficiently indicating branch target addresses. A semiconductor chip predecodes instructions of a computer program prior to installing the instructions in an instruction cache. In response to determining a particular instruction is a control flow instruction with a displacement relative to a program counter address (PC), the chip replaces a portion of the PC relative displacement in the particular instruction with a subset of a target address. The subset of the target address is an untranslated physical subset of the full target address. When the recoded particular instruction is fetched and decoded, the remaining portion of the PC relative displacement is added to a virtual portion of the PC used to fetch the particular instruction. The result is concatenated with the portion of the target address embedded in the fetched particular instruction to form a full target address.

Abstract translation: 一种有效指示分支目标地址的系统和方法。 在将指令安装到指令高速缓存之前，半导体芯片预先对计算机程序的指令进行解码。 响应于确定特定指令是具有相对于程序计数器地址（PC）的位移的控制流程指令，芯片用目标地址的子集替换特定指令中的PC相对位移的一部分。 目标地址的子集是完整目标地址的非翻译物理子集。 当重新编码的特定指令被取出和解码时，PC相对位移的剩余部分被添加到用于获取特定指令的PC的虚拟部分。 结果与嵌入在获取的特定指令中的目标地址的部分连接以形成完整的目标地址。

公开(公告)号：US20150169041A1

公开(公告)日：2015-06-18

申请号：US14104042

申请日：2013-12-12

Applicant: Apple Inc.

Inventor： Conrado Blasco ,  Ronald P. Hall ,  Ramesh B. Gunna ,  Ian D. Kountanis ,  Shyam Sundar ,  André Seznec

IPC: G06F1/32 ,  G06F9/38

CPC classification number: G06F1/3237 ,  G06F1/324 ,  G06F1/3275 ,  G06F1/3296 ,  G06F9/3802 ,  G06F9/3806 ,  Y02D10/126 ,  Y02D10/128 ,  Y02D10/14 ,  Y02D10/172

Abstract: A processor includes a mechanism for disabling a memory array of a branch prediction unit. The processor may include a next fetch prediction unit that may include a number of entries. Each entry may correspond to a next instruction fetch group and may store an indication of whether or not the corresponding the next fetch group includes a conditional branch instruction. In response to an indication that the next fetch group does not include a conditional branch instruction, the fetch prediction unit may be configured to disable, in a next instruction execution cycle, the memory array of the branch prediction unit.

Abstract translation: 处理器包括用于禁用分支预测单元的存储器阵列的机构。 处理器可以包括可以包括多个条目的下一个提取预测单元。 每个条目可以对应于下一个指令获取组，并且可以存储对应的下一个提取组是否包括条件分支指令的指示。 响应于下一个提取组不包括条件分支指令的指示，获取预测单元可以被配置为在下一个指令执行周期中禁止分支预测单元的存储器阵列。