公开(公告)号：US10445102B1

公开(公告)日：2019-10-15

申请号：US15707834

申请日：2017-09-18

Applicant: Apple Inc.

Inventor： Constantin Pistol ,  Ian D. Kountanis

IPC: G06F9/30 ,  G06F9/38

Abstract: Systems, apparatuses, and methods for efficient program flow prediction. After receiving a current fetch address, a first predictor performs a lookup of a first table. When the lookup results in a miss and the first table has no available entries, the first predictor overwrites a given entry of the first table with the received fetch address, in response to detecting a strength value for the given entry is below a threshold. Otherwise, in response to detecting no entries of the first table have a strength value below the threshold, the first predictor allocates an entry in the second table for the received fetch address. When an indication of a target address for the received fetch address is a return address for a function call, a third predictor allocates an entry of a third table with the received fetch address.

公开(公告)号：US10223123B1

公开(公告)日：2019-03-05

申请号：US15133804

申请日：2016-04-20

Applicant: Apple Inc.

Inventor： Conrado Blasco ,  Brett S. Feero ,  David Williamson ,  Ian D. Kountanis ,  Shih-Chieh Wen

IPC: G06F1/32 ,  G06F9/30 ,  G06F9/38 ,  G06F12/0875 ,  G06F1/3287 ,  G06F1/3234

Abstract: In an embodiment, an apparatus includes a plurality of memories configured to store respective data in a plurality of branch prediction entries. Each branch prediction entry corresponds to at least one of a plurality of branch instructions. The apparatus also includes a control circuit configured to store first data associated with a first branch instruction into a corresponding branch prediction entry in at least one memory of the plurality of memories. The control circuit is further configured to select a first memory of the plurality of memories, to disconnect the first memory from a power supply in response to a detection of a first power mode signal, and to cease storing data in the plurality of memories in response to the detection of the first power mode signal.

公开(公告)号：US09471322B2

公开(公告)日：2016-10-18

申请号：US14179204

申请日：2014-02-12

Applicant: Apple Inc.

Inventor： Conrado Blasco ,  Ian D. Kountanis

IPC: G06F9/30 ,  G06F9/38 ,  G06F1/32 ,  G06F9/32

CPC classification number: G06F9/381 ,  G06F1/3287 ,  G06F9/30058 ,  G06F9/30065 ,  G06F9/30189 ,  G06F9/325 ,  G06F9/3806 ,  G06F9/3844

Abstract: Systems, processors, and methods for determining when to enter loop buffer mode early for loops in an instruction stream. A processor waits until a branch history register has saturated before entering loop buffer mode for a loop if the processor has not yet determined the loop has an unpredictable exit. However, if the loop has an unpredictable exit, then the loop is allowed to enter loop buffer mode early. While in loop buffer mode, the loop is dispatched from a loop buffer, and the front-end of the processor is powered down until the loop terminates.

Abstract translation: 用于确定何时在指令流中循环进入循环缓冲模式的系统，处理器和方法。 如果处理器尚未确定循环具有不可预测的退出，处理器将等待直到分支历史寄存器在进入环路循环缓冲区模式之前饱和。 然而，如果循环有一个不可预测的退出，那么循环允许提前进入循环缓冲模式。 在循环缓冲模式下，循环从循环缓冲区中分派，处理器的前端掉电直到循环终止。

公开(公告)号：US20150169041A1

公开(公告)日：2015-06-18

申请号：US14104042

申请日：2013-12-12

Applicant: Apple Inc.

Inventor： Conrado Blasco ,  Ronald P. Hall ,  Ramesh B. Gunna ,  Ian D. Kountanis ,  Shyam Sundar ,  André Seznec

IPC: G06F1/32 ,  G06F9/38

CPC classification number: G06F1/3237 ,  G06F1/324 ,  G06F1/3275 ,  G06F1/3296 ,  G06F9/3802 ,  G06F9/3806 ,  Y02D10/126 ,  Y02D10/128 ,  Y02D10/14 ,  Y02D10/172

Abstract: A processor includes a mechanism for disabling a memory array of a branch prediction unit. The processor may include a next fetch prediction unit that may include a number of entries. Each entry may correspond to a next instruction fetch group and may store an indication of whether or not the corresponding the next fetch group includes a conditional branch instruction. In response to an indication that the next fetch group does not include a conditional branch instruction, the fetch prediction unit may be configured to disable, in a next instruction execution cycle, the memory array of the branch prediction unit.

Abstract translation: 处理器包括用于禁用分支预测单元的存储器阵列的机构。 处理器可以包括可以包括多个条目的下一个提取预测单元。 每个条目可以对应于下一个指令获取组，并且可以存储对应的下一个提取组是否包括条件分支指令的指示。 响应于下一个提取组不包括条件分支指令的指示，获取预测单元可以被配置为在下一个指令执行周期中禁止分支预测单元的存储器阵列。

公开(公告)号：US11630670B2

公开(公告)日：2023-04-18

申请号：US17382123

申请日：2021-07-21

Applicant: Apple Inc.

Inventor： Douglas C. Holman ,  Ian D. Kountanis ,  Amit Kumar ,  Muawya M. Al-Otoom

IPC: G06F9/38

Abstract: Techniques are disclosed relating to signature-based instruction prefetching. In some embodiments, processor pipeline circuitry executes a computer program that includes control transfer instructions, such that the execution follows a taken path through the computer program. First signature prefetch table circuitry indicates prefetch addresses for signatures generated using a first signature generation technique and second signature prefetch table circuitry indicates prefetch addresses for signatures generated using a second, different signature generation technique. Signature prefetch circuitry, in response to a prefetch training event, determines a first signature according to the first technique and a second signature according to the second technique and selects one but not both of the first and second signature prefetch tables to train using the first signature or the second signature.

公开(公告)号：US11468168B1

公开(公告)日：2022-10-11

申请号：US15484439

申请日：2017-04-11

Applicant: Apple Inc.

Inventor： Conrado Blasco ,  Ian D. Kountanis ,  Douglas C. Holman ,  Sean M. Reynolds ,  Richard F. Russo

IPC: G06F21/56 ,  G06F9/30 ,  G06F9/38 ,  G06F12/0875

Abstract: Systems, apparatuses, and methods for efficient handling of subroutine epilogues. When an indirect control transfer instruction corresponding to a procedure return for a subroutine is identified, the return address and a signature are retrieved from one or more of a return address stack and the memory stack. An authenticator generates a signature based on at least a portion of the retrieved return address. While the signature is being generated, instruction processing speculatively continues. No instructions are permitted to commit yet. The generated signature is later compared to a copy of the signature generated earlier during the corresponding procedure call. A mismatch causes an exception.

公开(公告)号：US11449343B2

公开(公告)日：2022-09-20

申请号：US16220488

申请日：2018-12-14

Applicant: Apple Inc.

Inventor： Jeffry E. Gonion ,  Ian D. Kountanis ,  Conrado Blasco ,  Steven Andrew Myers ,  Yannick L. Sierra

IPC: G06F9/38 ,  G06F21/60 ,  G06F9/455 ,  G06F9/30

Abstract: A system and method for efficiently protecting branch prediction information. In various embodiments, a computing system includes at least one processor with a branch predictor storing branch target addresses and security tags in a table. The security tag includes one or more components of machine context. When the branch predictor receives a portion of a first program counter of a first branch instruction, and hits on a first table entry during an access, the branch predictor reads out a first security tag. The branch predictor compares one or more components of machine context of the first security tag to one or more components of machine context of the first branch instruction. When there is at least one mismatch, the branch prediction information of the first table entry is not used. Additionally, there is no updating of any branch prediction training information of the first table entry.

公开(公告)号：US11093249B2

公开(公告)日：2021-08-17

申请号：US16292003

申请日：2019-03-04

Applicant: Apple Inc.

Inventor： Conrado Blasco ,  Brett S. Feero ,  David Williamson ,  Ian D. Kountanis ,  Shih-Chieh Wen

IPC: G06F9/38 ,  G06F9/30 ,  G06F1/3287 ,  G06F1/3234 ,  G06F1/3206 ,  G06F12/0875

Abstract: In an embodiment, an apparatus includes a plurality of memories configured to store respective data in a plurality of branch prediction entries. Each branch prediction entry corresponds to at least one of a plurality of branch instructions. The apparatus also includes a control circuit configured to store first data associated with a first branch instruction into a corresponding branch prediction entry in at least one memory of the plurality of memories. The control circuit is further configured to select a first memory of the plurality of memories, to disconnect the first memory from a power supply in response to a detection of a first power mode signal, and to cease storing data in the plurality of memories in response to the detection of the first power mode signal.

公开(公告)号：US20210240477A1

公开(公告)日：2021-08-05

申请号：US16778939

申请日：2020-01-31

Applicant: Apple Inc.

Inventor： Muawya M. Al-Otoom ,  Ian D. Kountanis ,  Conrado Blasco ,  Haoyan Jia ,  Amit Kumar

IPC: G06F9/38 ,  G06F9/30

Abstract: In an embodiment, an indirect branch predictor generates indirect branch predictions based on one or more register values. The register values may be the contents of registers on which the indirect branch instruction is directly or indirectly dependent for generating the branch target address, for example. In an embodiment, at least one of the registers may be a source for a load instruction, and the indirect branch may be dependent (directly or indirectly) on the target of the load. In an embodiment, the indirect branch predictor may be one of at least two indirect branch predictors in a processor. The other indirect branch predictor may be based on a fetch address, or PC, associated with the indirect branch instruction. The other indirect branch predictor may generate a first predicted target address, and the indirect branch predictor may generate a second predicted target address for the same indirect branch instruction.

公开(公告)号：US20190196834A1

公开(公告)日：2019-06-27

申请号：US16292003

申请日：2019-03-04

Applicant: Apple Inc.

Inventor： Conrado Blasco ,  Brett S. Feero ,  David Williamson ,  Ian D. Kountanis ,  Shih-Chieh Wen

IPC: G06F9/38 ,  G06F1/3287 ,  G06F1/3234 ,  G06F9/30 ,  G06F12/0875

CPC classification number: G06F9/3806 ,  G06F1/3275 ,  G06F1/3287 ,  G06F9/30058 ,  G06F12/0862 ,  G06F12/0875 ,  G06F2212/1024 ,  G06F2212/452

Abstract: In an embodiment, an apparatus includes a plurality of memories configured to store respective data in a plurality of branch prediction entries. Each branch prediction entry corresponds to at least one of a plurality of branch instructions. The apparatus also includes a control circuit configured to store first data associated with a first branch instruction into a corresponding branch prediction entry in at least one memory of the plurality of memories. The control circuit is further configured to select a first memory of the plurality of memories, to disconnect the first memory from a power supply in response to a detection of a first power mode signal, and to cease storing data in the plurality of memories in response to the detection of the first power mode signal.