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    ORDERING MEMORY REQUESTS BASED ON ACCESS EFFICIENCY
    21.
    发明申请
    ORDERING MEMORY REQUESTS BASED ON ACCESS EFFICIENCY 审中-公开

    公开(公告)号：US20200065028A1

    公开(公告)日：2020-02-27

    申请号：US16112624

    申请日：2018-08-24

    Applicant: Apple Inc.

    Inventor： Shane J. Keil ,  Gregory S. Mathews ,  Lakshmi Narasimha Murthy Nukala ,  Thejasvi Magudilu Vijayaraj ,  Kai Lun Hsiung ,  Yanzhe Liu ,  Sukalpa Biswas

    IPC: G06F3/06

    Abstract: An embodiment of an apparatus includes a memory circuit and a memory controller circuit. The memory controller circuit may include a write request queue. The memory controller circuit may be configured to receive a memory request to access the memory circuit and determine if the memory request includes a read request or a write request. A received read request may be scheduled for execution, while a received write request may be stored in the write request queue. The memory controller circuit may reorder scheduled memory requests based on achieving a specified memory access efficiency and based on a number of write requests stored in the write request queue.

    Read arbiter circuit with dual memory rank support
    22.
    发明授权
    Read arbiter circuit with dual memory rank support 有权

    公开(公告)号：US12216594B2

    公开(公告)日：2025-02-04

    申请号：US18469905

    申请日：2023-09-19

    Applicant: Apple Inc.

    Inventor： Shane J. Keil ,  Gregory S. Mathews ,  Lakshmi Narasimha Murthy Nukala

    IPC: G06F13/16

    Abstract: A memory control circuit coupled to multiple memory ranks may receive read and write requests for a different ranks of the multiple memory ranks. The memory control may allocate write requests to different slots based on the write requests target memory rank, and may adjust the number of slots available for a given memory rank during a write turn to improve write efficiency. The memory control circuit may also determine a number of ranks switches within a read turn based on whether a particular quality-of-service requirement associated with the read requests is being satisfied.

    Memory Device Bandwidth Optimization
    24.
    发明公开
    Memory Device Bandwidth Optimization 审中-公开

    公开(公告)号：US20240202146A1

    公开(公告)日：2024-06-20

    申请号：US18588406

    申请日：2024-02-27

    Applicant: Apple Inc.

    Inventor： Gregory S. Mathews ,  Shane J. Keil

    IPC: G06F13/16 ,  G06F1/06

    CPC classification number: G06F13/1684 ,  G06F1/06 ,  G06F13/1647

    Abstract: Techniques for scheduling memory operations are disclosed in which alternate read/write commands within a multi-bank memory operation are delayed beyond a minimum timing parameter in order to increase memory data bus utilization. The remaining read/write commands are not delayed beyond the minimum timing parameter. Every other clock cycle (e.g., even clock cycles) within the memory operation is reserved for activate commands, while other commands such as sync and read/write are scheduled on the intervening clock cycles (e.g., odd clock cycles). For memory devices for which a sync command (which causes a clock of the memory data bus to start) is to precede a corresponding read/write command by a number of clock cycles that would place it in a cycle reserved for activate commands, a particular operation mode is disclosed in which the memory device internally delays a received sync command.

    Memory device bandwidth optimization
    25.
    发明授权
    Memory device bandwidth optimization 有权

    公开(公告)号：US11914532B2

    公开(公告)日：2024-02-27

    申请号：US17655324

    申请日：2022-03-17

    Applicant: Apple Inc.

    Inventor： Gregory S. Mathews ,  Shane J. Keil

    IPC: G06F13/16 ,  G06F1/06

    CPC classification number: G06F13/1684 ,  G06F1/06 ,  G06F13/1647

    Abstract: Techniques for scheduling memory operations are disclosed in which alternate read/write commands within a multi-bank memory operation are delayed beyond a minimum timing parameter in order to increase memory data bus utilization. The remaining read/write commands are not delayed beyond the minimum timing parameter. Every other clock cycle (e.g., even clock cycles) within the memory operation is reserved for activate commands, while other commands such as sync and read/write are scheduled on the intervening clock cycles (e.g., odd clock cycles). For memory devices for which a sync command (which causes a clock of the memory data bus to start) is to precede a corresponding read/write command by a number of clock cycles that would place it in a cycle reserved for activate commands, a particular operation mode is disclosed in which the memory device internally delays a received sync command.

    Multi-activation techniques for partial write operations
    26.
    发明授权
    Multi-activation techniques for partial write operations 有权

    公开(公告)号：US11847348B2

    公开(公告)日：2023-12-19

    申请号：US17410657

    申请日：2021-08-24

    Applicant: Apple Inc.

    Inventor： Shane J. Keil ,  Gregory S. Mathews ,  Lakshmi Narasimha Murthy Nukala

    IPC: G06F3/06

    CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0676 ,  G06F3/0677 ,  G06F3/0679

    Abstract: Techniques are disclosed relating to multi-activation techniques for wire operations with multiple partial writes. In some embodiments, a memory controller is configured to access data in a memory device that supports partial writes having a first size using read-modify-write operations and non-partial writes having a second size that is greater than the first size. In some embodiments, the memory controller is configured to queue a first write operation having the second size, where the first write operation includes multiple partial writes. In some embodiments, the memory controller is configured to send separate activate signals to the memory device to activate a bank of the memory device to perform different proper subsets of the multiple partial writes. This may allow interleaving of other accesses to a memory bank and merging of writes while waiting for a current activation, in some embodiments.

    Communication channels with both shared and independent resources
    27.
    发明授权
    Communication channels with both shared and independent resources 有权

    公开(公告)号：US11824795B2

    公开(公告)日：2023-11-21

    申请号：US17455321

    申请日：2021-11-17

    Applicant: Apple Inc.

    Inventor： Rohit K. Gupta ,  Gregory S. Mathews ,  Harshavardhan Kaushikkar ,  Jeonghee Shin ,  Rohit Natarajan

    IPC: H04L12/801 ,  H04L47/80 ,  H04L47/25 ,  H04L47/10

    CPC classification number: H04L47/805 ,  H04L47/25 ,  H04L47/39

    Abstract: Techniques are disclosed relating to merging virtual communication channels in a portion of a computing system. In some embodiments, a communication fabric routes first and second classes of traffic with different quality-of-service parameters, using a first virtual channel for the first class and a second virtual channel for the second class. In some embodiments, a memory controller communicates, via the fabric, using a merged virtual channel configured to handle traffic from both the first virtual channel and the second virtual channel. In some embodiments, the system limits the rate at which an agent is allowed to transmit requests of the second class of traffic, but requests by the agent for the first class of traffic are not rate limited. Disclosed techniques may improve independence of virtual channels, relative to sharing the same channel in an entire system, without unduly increasing complexity.

    Decoding Status Flag Techniques for Memory Circuits
    28.
    发明公开
    Decoding Status Flag Techniques for Memory Circuits 审中-公开

    公开(公告)号：US20230325274A1

    公开(公告)日：2023-10-12

    申请号：US18323178

    申请日：2023-05-24

    Applicant: Apple Inc.

    Inventor： Farid Nemati ,  Steven R. Hutsell ,  Gregory S. Mathews ,  Yi Chun Chen ,  Kevin C. Wong ,  Kalpana Bansal

    IPC: G06F11/07 ,  G06F11/10

    CPC classification number: G06F11/1064 ,  G06F11/076 ,  G06F11/0772 ,  G06F11/106

    Abstract: Techniques are disclosed relating to improving memory reliability. In some embodiments, memory circuitry includes memory cells configured to store data, interface circuitry, and on-die error correcting code (ECC) circuitry. The ECC circuitry may check read data from the memory cells for errors and correct detected correctable errors to generate corrected data. The memory circuitry may provide read data to a requesting circuit via the interface circuitry, including one or more sets of corrected data from the on-die ECC circuitry. The memory circuitry may provide a decoding status flag (DSF) via the interface circuitry, including to: set the DSF to a first value in response to no error being detected for a given set of provided read data, set the DSF to a second value in response to a correctable error that was detected and corrected by the on-die ECC circuitry to provide a given set of read data, and set the DSF to a third value in response to an uncorrectable error detected by the on-die ECC circuitry.

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