公开(公告)号：US20220197827A1

公开(公告)日：2022-06-23

申请号：US17125978

申请日：2020-12-17

Applicant: Advanced Micro Devices, Inc.

Inventor： Sudhanva Gurumurthi ,  Vilas K. Sridharan

IPC: G06F12/14 ,  G06F12/1009 ,  G06F12/0882 ,  G06F12/0871 ,  G06F21/79

Abstract: A method and system for memory attack mitigation in a memory device includes receiving, at a memory controller, an allocation of a page in memory. One or more device controllers detects an aggressor-victim set within the memory. Based upon the detection, an address of the allocated page is identified for further action.

公开(公告)号：US09734059B2

公开(公告)日：2017-08-15

申请号：US13945659

申请日：2013-07-18

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Lena E. Olson ,  Yasuko Eckert ,  Vilas K. Sridharan ,  James M. O'Connor ,  Mark D. Hill ,  Srilatha Manne

IPC: G06F12/08 ,  G06F12/0802 ,  G06F12/0875 ,  G06F12/123 ,  G06F12/0846 ,  G06F12/0864 ,  G06F12/0862

CPC classification number: G06F12/0802 ,  G06F12/0848 ,  G06F12/0862 ,  G06F12/0864 ,  G06F12/0875 ,  G06F12/123 ,  G06F2212/1016 ,  G06F2212/1028 ,  G06F2212/451 ,  G06F2212/502 ,  G06F2212/601 ,  G06F2212/6032 ,  G06F2212/6082 ,  Y02D10/13

Abstract: A method of way prediction for a data cache having a plurality of ways is provided. Responsive to an instruction to access a stack data block, the method accesses identifying information associated with a plurality of most recently accessed ways of a data cache to determine whether the stack data block resides in one of the plurality of most recently accessed ways of the data cache, wherein the identifying information is accessed from a subset of an array of identifying information corresponding to the plurality of most recently accessed ways; and when the stack data block resides in one of the plurality of most recently accessed ways of the data cache, the method accesses the stack data block from the data cache.

公开(公告)号：US09106260B2

公开(公告)日：2015-08-11

申请号：US13720504

申请日：2012-12-19

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： James M. O'Connor ,  Vilas K. Sridharan ,  Gabriel H. Loh

IPC: H03M13/11 ,  G06F11/00 ,  H03M13/53 ,  H03M13/05

CPC classification number: H03M13/11 ,  G06F11/00 ,  G06F11/1048 ,  H03M13/05

Abstract: A processor system as presented herein includes a processor core, cache memory coupled to the processor core, a memory controller coupled to the cache memory, and a system memory component coupled to the memory controller. The system memory component includes a plurality of independent memory channels configured to store data blocks, wherein the memory controller controls the storing of parity bits in at least one of the plurality of independent memory channels. In some implementations, the system memory is realized as a die-stacked memory component.

Abstract translation: 如本文所述的处理器系统包括处理器核心，耦合到处理器核心的高速缓存存储器，耦合到高速缓冲存储器的存储器控​​制器以及耦合到存储器控制器的系统存储器组件。 系统存储器组件包括被配置为存储数据块的多个独立存储器通道，其中存储器控制器控制在多个独立存储器通道中的至少一个中存储奇偶校验位。 在一些实现中，系统存储器被实现为管芯堆叠的存储器组件。

公开(公告)号：US08984368B2

公开(公告)日：2015-03-17

申请号：US13649745

申请日：2012-10-11

Applicant: Advanced Micro Devices, Inc.

Inventor： Gabriel H. Loh ,  Vilas K. Sridharan

IPC: G11C29/00 ,  G06F11/10

CPC classification number: G06F11/1044

Abstract: An integrated circuit includes a memory having an address space and a memory controller coupled to the memory for accessing the address space in response to received memory accesses. The memory controller further accesses a plurality of data elements in a first portion of the address space, and reliability data corresponding to the plurality of data elements in a second portion of the address space.

Abstract translation: 集成电路包括具有地址空间的存储器和耦合到存储器的存储器控​​制器，用于响应于接收到的存储器访问来访问地址空间。 存储器控制器还访问地址空间的第一部分中的多个数据元素以及与地址空间的第二部分中的多个数据元素相对应的可靠性数据。

公开(公告)号：US20140173378A1

公开(公告)日：2014-06-19

申请号：US13720504

申请日：2012-12-19

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： James M. O'Connor ,  Vilas K. Sridharan ,  Gabriel H. Loh

IPC: H03M13/11

CPC classification number: H03M13/11 ,  G06F11/00 ,  G06F11/1048 ,  H03M13/05

Abstract: A processor system as presented herein includes a processor core, cache memory coupled to the processor core, a memory controller coupled to the cache memory, and a system memory component coupled to the memory controller. The system memory component includes a plurality of independent memory channels configured to store data blocks, wherein the memory controller controls the storing of parity bits in at least one of the plurality of independent memory channels. In some implementations, the system memory is realized as a die-stacked memory component.

Abstract translation: 如本文所述的处理器系统包括处理器核心，耦合到处理器核心的高速缓存存储器，耦合到高速缓冲存储器的存储器控​​制器以及耦合到存储器控制器的系统存储器组件。 系统存储器组件包括被配置为存储数据块的多个独立存储器通道，其中存储器控制器控制在多个独立存储器通道中的至少一个中存储奇偶校验位。 在一些实现中，系统存储器被实现为管芯堆叠的存储器组件。

公开(公告)号：US20140143499A1

公开(公告)日：2014-05-22

申请号：US13945659

申请日：2013-07-18

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Lena E. Olson ,  Yasuko Eckert ,  Vilas K. Sridharan ,  James M. O'Connor ,  Mark D. Hill ,  Srilatha Manne

IPC: G06F12/12 ,  G06F12/08

CPC classification number: G06F12/0802 ,  G06F12/0848 ,  G06F12/0862 ,  G06F12/0864 ,  G06F12/0875 ,  G06F12/123 ,  G06F2212/1016 ,  G06F2212/1028 ,  G06F2212/451 ,  G06F2212/502 ,  G06F2212/601 ,  G06F2212/6032 ,  G06F2212/6082 ,  Y02D10/13

Abstract: A method of way prediction for a data cache having a plurality of ways is provided. Responsive to an instruction to access a stack data block, the method accesses identifying information associated with a plurality of most recently accessed ways of a data cache to determine whether the stack data block resides in one of the plurality of most recently accessed ways of the data cache, wherein the identifying information is accessed from a subset of an array of identifying information corresponding to the plurality of most recently accessed ways; and when the stack data block resides in one of the plurality of most recently accessed ways of the data cache, the method accesses the stack data block from the data cache.

Abstract translation: 提供了一种具有多种方式的数据高速缓存的方式预测方法。 响应于访问堆栈数据块的指令，该方法访问与数据高速缓存的多个最近访问的方式相关联的识别信息，以确定堆栈数据块是否位于数据的多个最近访问的方式之一 高速缓存，其中从与多个最近访问的方式对应的识别信息的数组的子集中访问所述识别信息; 并且当堆栈数据块驻留在数据高速缓存的多个最近被访问的方式之一时，该方法从数据高速缓存访​​问堆栈数据块。