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    OFFSET-ALIGNED THREE-DIMENSIONAL INTEGRATED CIRCUIT
    21.
    发明申请
    OFFSET-ALIGNED THREE-DIMENSIONAL INTEGRATED CIRCUIT 有权

    公开(公告)号：US20220392882A1

    公开(公告)日：2022-12-08

    申请号：US17891444

    申请日：2022-08-19

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Brett P. Wilkerson ,  Milind S. Bhagavat ,  Rahul Agarwal ,  Dmitri Yudanov

    IPC: H01L25/18 ,  H01L23/367 ,  H01L23/00 ,  H01L25/00 ,  H01L23/48

    Abstract: A three-dimensional integrated circuit includes a first die structure having a first geometry. The first die structure includes a first region that operates with a first power density and a second region that operates with a second power density. The first power density is less than the second power density. The three-dimensional integrated circuit includes a second die structure having a second geometry. A stacked portion of the second die structure is aligned with the first region. The three-dimensional integrated circuit includes an additional die structure stacked with the first die structure and the second die structure. The additional die structure has the first geometry or the second geometry.

    Semiconductor package with annular package lid structure
    23.
    发明授权
    Semiconductor package with annular package lid structure 有权

    公开(公告)号：US12278150B2

    公开(公告)日：2025-04-15

    申请号：US17490943

    申请日：2021-09-30

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： Priyal Shah ,  Brett P. Wilkerson ,  Raja Swaminathan

    IPC: H01L23/053 ,  H01L21/48 ,  H01L21/52 ,  H01L23/367 ,  H01L23/498

    Abstract: A semiconductor package includes a substrate having opposing first and second surfaces as well as a semiconductor chip component disposed at the second surface and having third and fourth opposing surfaces. A package lid structure is affixed to the second surface of the substrate and the fourth surface of the semiconductor chip component, and has a planar component overlying the semiconductor chip component and having a fifth surface facing the fourth surface and an opposing sixth surface. The planar component includes an aperture extending between the fifth surface and the sixth surface so as to expose at least a portion of the fourth surface of the semiconductor chip component. A thermal exchange structure can be mounted on the package lid structure to form a thermal extraction pathway with the semiconductor die component via the aperture, either directly or via an interposing thermally conductive plate.

    3D semiconductor package with die-mounted voltage regulator
    26.
    发明授权
    3D semiconductor package with die-mounted voltage regulator 有权

    公开(公告)号：US12165981B2

    公开(公告)日：2024-12-10

    申请号：US17556346

    申请日：2021-12-20

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： Gabriel H Loh ,  Raja Swaminathan ,  Rahul Agarwal ,  Brett P. Wilkerson

    IPC: H01L23/538 ,  G05F1/575 ,  H01L25/065 ,  H01L27/06

    Abstract: A semiconductor package includes a package substrate having a first surface and an opposing second surface, and further includes an integrated circuit (IC) die disposed at the second surface and having a third surface facing the second surface and an opposing fourth surface. The IC die has a first region comprising one or more metal layers and circuit components for one or more functions of the IC die and a second region offset from the first region in a direction parallel with the third and fourth surfaces. The semiconductor package further includes a voltage regulator disposed at the fourth surface in the second region and having an input configured to receive a supply voltage and an output configured to provide a regulated voltage, and also includes a conductive path coupling the output of the voltage regulator to a voltage input of circuitry of the IC die.

    Molded chip package with anchor structures
    28.
    发明授权
    Molded chip package with anchor structures 有权

    公开(公告)号：US11367628B2

    公开(公告)日：2022-06-21

    申请号：US16513450

    申请日：2019-07-16

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： Priyal Shah ,  Milind S. Bhagavat ,  Brett P. Wilkerson ,  Lei Fu ,  Rahul Agarwal

    IPC: H01L21/56 ,  H01L23/31

    Abstract: Various semiconductor chip packages are disclosed. In one aspect, a semiconductor chip package includes a package substrate that has a first side and a second side opposite to the first side. A semiconductor chip is mounted on the first side. Plural metal anchor structures are coupled to the package substrate and project away from the first side. A molding layer is on the package substrate and at least partially encapsulates the semiconductor chip and the anchor structures. The anchor structures terminate in the molding layer and anchor the molding layer to the package substrate.

    OFFSET-ALIGNED THREE-DIMENSIONAL INTEGRATED CIRCUIT
    30.
    发明申请
    OFFSET-ALIGNED THREE-DIMENSIONAL INTEGRATED CIRCUIT 审中-公开

    公开(公告)号：US20190326272A1

    公开(公告)日：2019-10-24

    申请号：US15958169

    申请日：2018-04-20

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Brett P. Wilkerson ,  Milind Bhagavat ,  Rahul Agarwal ,  Dmitri Yudanov

    IPC: H01L25/18 ,  H01L23/48 ,  H01L23/367 ,  H01L23/00 ,  H01L25/00

    Abstract: A three-dimensional integrated circuit includes a first die having a first geometry. The first die includes a first region that operates with a first power density and a second region that operates with a second power density. The first power density is less than the second power density. The first die includes first electrical contacts disposed in the first region on a first side of the first die along a periphery of the first die. The three-dimensional integrated circuit includes a second die having a second geometry. The second die includes second electrical contacts disposed on a first side of the second die. A stacked portion of the second die is stacked within the periphery of the first die and an overhang portion of the second die extends beyond the periphery of the first die. The second electrical contacts are aligned with and coupled to the first electrical contacts.

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