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    Parameter FIFO
    22.
    发明授权
    Parameter FIFO 有权
    参数FIFO

    公开(公告)号：US09262798B2

    公开(公告)日：2016-02-16

    申请号：US14263424

    申请日：2014-04-28

    Applicant: Apple Inc.

    Inventor： Joseph P. Bratt ,  Peter F. Holland ,  Shing Horng Choo ,  Timothy J. Millet

    IPC: G09G5/39 ,  G06T1/60 ,  G09G5/36 ,  G09G5/14

    CPC classification number: G06T1/60 ,  G09G5/14 ,  G09G5/363 ,  G09G2340/10 ,  G09G2360/12 ,  G09G2360/127

    Abstract: A graphics system may include one or more processing units for processing a current display frame, each processing unit including a plurality of parameter registers for storing parameter settings used in processing the current display frame. A parameter buffer in the graphics system may store frame packets, with each frame packet containing information corresponding to parameter settings to be used for at least one display frame. A control circuit coupled to the buffer and to the one or more processing units may retrieve and process a top frame packet from the parameter buffer to update one or more of the parameter registers according to the contents of the top frame packet. The control circuit may issue DMA requests to fill the parameter buffer with frame packets transferred from system memory, where the frame packets may be written by an application (or software) executing on a central processing unit.

    Abstract translation: 图形系统可以包括用于处理当前显示帧的一个或多个处理单元，每个处理单元包括用于存储用于处理当前显示帧的参数设置的多个参数寄存器。 图形系统中的参数缓冲器可以存储帧分组，每个帧分组包含对应于要用于至少一个显示帧的参数设置的信息。 耦合到缓冲器和一个或多个处理单元的控制电路可以从参数缓冲器检索和处理顶部帧分组，以根据顶部帧分组的内容更新一个或多个参数寄存器。 控制电路可以发出DMA请求，用从系统存储器传送的帧分组填充参数缓冲器，其中帧分组可以由在中央处理单元上执行的应用（或软件）写入。

    Streaming translation in display pipe
    23.
    发明授权
    Streaming translation in display pipe 有权
    在显示管道中进行流式翻译

    公开(公告)号：US08994741B2

    公开(公告)日：2015-03-31

    申请号：US13776945

    申请日：2013-02-26

    Applicant: Apple Inc.

    Inventor： Joseph P. Bratt ,  Peter F. Holland

    IPC: G06F12/10 ,  G06F12/02 ,  G06F12/08 ,  G06F12/12

    CPC classification number: G06F12/0215 ,  G06F12/0802 ,  G06F12/0862 ,  G06F12/1027 ,  G06F12/123 ,  G06F2212/302 ,  G06F2212/654

    Abstract: In an embodiment, a display pipe includes one or more translation units corresponding to images that the display pipe is reading for display. Each translation unit may be configured to prefetch translations ahead of the image data fetches, which may prevent translation misses in the display pipe (at least in most cases). The translation units may maintain translations in first-in, first-out (FIFO) fashion, and the display pipe fetch hardware may inform the translation unit when a given translation or translation is no longer needed. The translation unit may invalidate the identified translations and prefetch additional translation for virtual pages that are contiguous with the most recently prefetched virtual page.

    Abstract translation: 在一个实施例中，显示管道包括与显示管正在读取以供显示的图像对应的一个或多个平移单元。 每个翻译单元可以被配置为在图像数据提取之前预取翻译，这可以防止显示管道中的翻译缺失（至少在大多数情况下）。 翻译单元可以以先入先出（FIFO）方式保持翻译，并且显示管取出硬件可以在不再需要给定的翻译或翻译时通知翻译单元。 翻译单元可以使所识别的翻译失效，并且为与最近预取的虚拟页面连续的虚拟页面预取附加翻译。

    Buffer Underrun Handling
    24.
    发明申请
    Buffer Underrun Handling 审中-公开
    缓冲区欠载处理

    公开(公告)号：US20140139535A1

    公开(公告)日：2014-05-22

    申请号：US14163326

    申请日：2014-01-24

    Applicant: Apple Inc.

    Inventor： Joseph P. Bratt ,  Peter F. Holland ,  Shing Horng Choo ,  Timothy J. Millet ,  Brijesh Tripathi

    IPC: G06T1/60

    CPC classification number: G06T1/60 ,  G09G5/39

    Abstract: A graphics system may include a display pipe with a buffer configured to store pixels to be processed by a display controller for displaying on a display device, with a buffer control circuit coupled to the buffer to supply pixels to the display controller. When the buffer control circuit detects an underrun of the buffer responsive to the display controller attempting to read pixels from the buffer that have not yet been written to the buffer, the buffer control circuit may supply an underrun pixel to the display. The underrun pixel may be selected from a set of previously stored set of underrun pixels, which may include a most recent valid pixel read by the display controller. A read pointer representative of the location in the buffer from where the display controller is currently attempting to read may be advanced even when an underrun condition occurs. The underrun pixel may be supplied to the display controller until the underrun has been resolved, at which point the most recent valid pixel read from the buffer may be supplied to the display controller.

    Abstract translation: 图形系统可以包括具有缓冲器的显示管道，缓冲器被配置为存储要由显示控制器处理的像素，用于在显示设备上显示，缓冲器控制电路耦合到缓冲器以向显示控制器提供像素。 当缓冲器控制电路响应于显示控制器尝试读取尚未写入缓冲器的缓冲器的像素时，缓冲器控制电路检测到欠载，缓冲器控制电路可以向显示器提供欠载像素。 欠载像素可以从先前存储的欠载像素组中选择，其可以包括由显示控制器读取的最新有效像素。 即使在出现欠载条件的情况下，代表显示控制器当前尝试读取的缓冲器中的位置的读取指针也可以被提前。 欠载像素可以被提供给显示控制器，直到欠载已被解析为止，此时从缓冲器读取的最新的有效像素可以被提供给显示控制器。

    BIPOLAR COLLAPSIBLE FIFO
    25.
    发明申请
    BIPOLAR COLLAPSIBLE FIFO 审中-公开

    公开(公告)号：US20140089604A1

    公开(公告)日：2014-03-27

    申请号：US13629100

    申请日：2012-09-27

    Applicant: APPLE INC.

    Inventor： Peter F. Holland ,  Albert C. Kuo ,  Joseph P. Bratt

    IPC: G06F12/00

    CPC classification number: G06F9/5016 ,  G06F9/5022 ,  Y02D10/22

    Abstract: A system and method for efficient dynamic utilization of shared resources. A computing system includes a shared buffer accessed by two requestors generating access requests. Any entry within the shared buffer may be allocated for use by a first requestor or a second requestor. The storage buffer stores received indications of access requests from the first requestor beginning at a first end of the storage buffer. The storage buffer stores received indications of access requests from the second requestor beginning at a second end of the storage buffer. The storage buffer maintains an oldest stored indication of an access request for the first requestor at the first end and an oldest stored indication of an access request for the second requestor at the second end. The shared buffer deallocates in-order of age from oldest to youngest allocated entries corresponding to a given requestor of the first requestor and the second requestor.

    Abstract translation: 一种有效动态利用共享资源的系统和方法。 计算系统包括由生成访问请求的两个请求者访问的共享缓冲器。 共享缓冲器中的任何条目可以被分配供第一请求者或第二请求者使用。 存储缓冲器存储从存储缓冲器的第一端开始的来自第一请求者的接收请求的接收指示。 存储缓冲器从存储缓冲器的第二端开始存储来自第二请求者的访问请求的接收指示。 存储缓冲器在第一端保持对第一请求者的访问请求的最旧的存储指示，并且在第二端维护对于第二请求者的访问请求的最早存储的指示。 共享缓冲器按照与第一请求者和第二请求者的给定请求者相对应的从最旧到最小分配条目的时间顺序取消分配。

    Streaming Translation in Display Pipe
    26.
    发明申请
    Streaming Translation in Display Pipe 审中-公开
    流媒体显示管道翻译

    公开(公告)号：US20130179638A1

    公开(公告)日：2013-07-11

    申请号：US13776945

    申请日：2013-02-26

    Applicant: Apple Inc.

    Inventor： Joseph P. Bratt ,  Peter F. Holland

    IPC: G06F12/02 ,  G06F12/08

    CPC classification number: G06F12/0215 ,  G06F12/0802 ,  G06F12/0862 ,  G06F12/1027 ,  G06F12/123 ,  G06F2212/302 ,  G06F2212/654

    Abstract: In an embodiment, a display pipe includes one or more translation units corresponding to images that the display pipe is reading for display. Each translation unit may be configured to prefetch translations ahead of the image data fetches, which may prevent translation misses in the display pipe (at least in most cases). The translation units may maintain translations in first-in, first-out (FIFO) fashion, and the display pipe fetch hardware may inform the translation unit when a given translation or translation is no longer needed. The translation unit may invalidate the identified translations and prefetch additional translation for virtual pages that are contiguous with the most recently prefetched virtual page.

    Abstract translation: 在一个实施例中，显示管道包括与显示管正在读取以供显示的图像对应的一个或多个平移单元。 每个翻译单元可以被配置为在图像数据提取之前预取翻译，这可以防止显示管道中的翻译缺失（至少在大多数情况下）。 翻译单元可以以先入先出（FIFO）方式保持翻译，并且显示管取出硬件可以在不再需要给定的翻译或翻译时通知翻译单元。 翻译单元可以使所识别的翻译失效，并且为与最近预取的虚拟页面连续的虚拟页面预取附加翻译。

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