公开(公告)号：US20190268086A1

公开(公告)日：2019-08-29

申请号：US15903253

申请日：2018-02-23

Applicant: Advanced Micro Devices, Inc.

Inventor： John Wuu ,  Samuel Naffziger ,  Michael K. Ciraula ,  Russell Schreiber

IPC: H04J99/00 ,  H01L23/48 ,  H01L23/00

Abstract: An integrated circuit includes first and second through-silicon via (TSV) circuits and a steering logic circuit. The first TSV circuit has a first TSV and a first multiplexer for selecting between a first TSV data signal received from the first TSV and a first local data signal for transmission to a first TSV output terminal. The second TSV circuit includes a second TSV and a second multiplexer for selecting between a second TSV data signal received from the second TSV and the first local data signal for transmission to a second TSV output terminal. The steering logic circuit controls the first multiplexer to select the first local data signal and the second multiplexer to select the second TSV data signal in a first mode, and the first multiplexer to select the first TSV data signal and the second multiplexer to select the first local data signal in a second mode.

公开(公告)号：US20150106642A1

公开(公告)日：2015-04-16

申请号：US14053315

申请日：2013-10-14

Applicant: Advanced Micro Devices, Inc.

Inventor： Samuel Naffziger ,  Baomin Liu ,  Maxat Touzelbaev

IPC: G06F1/26

CPC classification number: G06F1/26 ,  G06F1/206 ,  G06F1/3206 ,  G06F1/324 ,  Y02D10/126 ,  Y02D10/16

Abstract: An integrated circuit includes a multiple number of processor cores and a system management unit. The multiple number of processor cores each operate at one of a multiple number of performance states. The system management unit is coupled to the multiple number of processor cores, for setting performance states of the multiple number of processor cores. The system management unit boosts a first performance state of a first processor core of the multiple number of processor cores based on both a first temperature calculated from an estimated power consumption, and a second temperature based on a temperature measurement.

Abstract translation: 集成电路包括多个处理器核和系统管理单元。 多个处理器核心各自以多个性能状态中的一个操作。 系统管理单元耦合到多个处理器核心，用于设置多个处理器核心的性能状态。 系统管理单元基于从估计的功耗计算出的第一温度和基于温度测量的第二温度来提高多个处理器核心的第一处理器核心的第一性能状态。

公开(公告)号：US20240321706A1

公开(公告)日：2024-09-26

申请号：US18474151

申请日：2023-09-25

Applicant: Advanced Micro Devices, Inc.

Inventor： William George En ,  Samuel Naffziger ,  Regina T. Schmidt ,  Omar Zia ,  John Wuu

IPC: H01L23/498 ,  H01L23/48 ,  H01L25/065

CPC classification number: H01L23/49827 ,  H01L23/481 ,  H01L23/49816 ,  H01L25/0657 ,  H01L2225/06541

Abstract: A method for implementing shared metal connectivity between 3D stacked circuit dies can include providing a first circuit die having a first metal stack. The method can additionally include providing a second circuit die having a second metal stack, wherein at least one metal layer of the second metal stack is utilized by both the first circuit die and the second circuit die. The method can also include connecting the second metal stack to the first metal stack of the first circuit die. Various other methods, systems, and computer-readable media are also disclosed.

公开(公告)号：US11164807B2

公开(公告)日：2021-11-02

申请号：US16563077

申请日：2019-09-06

Applicant: Advanced Micro Devices, Inc.

Inventor： John Wuu ,  Samuel Naffziger ,  Patrick J. Shyvers ,  Milind S. Bhagavat ,  Kaushik Mysore ,  Brett P. Wilkerson

IPC: H01L23/367 ,  H01L25/00 ,  H01L25/065 ,  H01L23/36 ,  H01L23/373

Abstract: Various semiconductor chip devices with stacked chips are disclosed. In one aspect, a semiconductor chip device is provided. The semiconductor chip device includes a first semiconductor chip that has a floor plan with a high heat producing area and a low heat producing area. At least one second semiconductor chip is stacked on the low heat producing area. The semiconductor chip device also includes means for transferring heat from the high heat producing area.

公开(公告)号：US09772676B2

公开(公告)日：2017-09-26

申请号：US14190803

申请日：2014-02-26

Applicant: Advanced Micro Devices, Inc.

Inventor： Stephen Kosonocky ,  Samuel Naffziger

IPC: G06F1/00 ,  G06F1/32 ,  G06F1/20

CPC classification number: G06F1/3296 ,  G06F1/206 ,  G06F1/3206 ,  Y02D10/16 ,  Y02D10/172

Abstract: Some embodiments of a processing device include one or more power supply monitors to provide one or more counts representative of one or more operating frequencies of one or more circuit blocks based on a voltage supplied to the circuit block(s). Some embodiments of the processing device also include a system management unit to determine an initial voltage supplied to the circuit block(s) based on a target count and to reduce the voltage supplied to the circuit block(s) from the initial voltage in response to the count(s) generated by the power supply monitor(s) exceeding the target count.

公开(公告)号：US09483092B2

公开(公告)日：2016-11-01

申请号：US14053315

申请日：2013-10-14

Applicant: Advanced Micro Devices, Inc.

Inventor： Samuel Naffziger ,  Baomin Liu ,  Maxat Touzelbaev

IPC: G06F1/26 ,  G06F1/32

CPC classification number: G06F1/26 ,  G06F1/206 ,  G06F1/3206 ,  G06F1/324 ,  Y02D10/126 ,  Y02D10/16

Abstract: An integrated circuit includes a multiple number of processor cores and a system management unit. The multiple number of processor cores each operate at one of a multiple number of performance states. The system management unit is coupled to the multiple number of processor cores, for setting performance states of the multiple number of processor cores. The system management unit boosts a first performance state of a first processor core of the multiple number of processor cores based on both a first temperature calculated from an estimated power consumption, and a second temperature based on a temperature measurement.

Abstract translation: 集成电路包括多个处理器核和系统管理单元。 多个处理器核心各自以多个性能状态中的一个操作。 系统管理单元耦合到多个处理器核心，用于设置多个处理器核心的性能状态。 系统管理单元基于从估计的功耗计算出的第一温度和基于温度测量的第二温度来提高多个处理器核心的第一处理器核心的第一性能状态。

公开(公告)号：US09170631B2

公开(公告)日：2015-10-27

申请号：US13759611

申请日：2013-02-05

Applicant: Advanced Micro Devices, Inc.

Inventor： Samuel Naffziger ,  Bao-min Liu

IPC: G06F1/00 ,  G06F1/32

CPC classification number: G06F1/3206 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

Abstract: Methods, apparatus, and fabrication processes relating to thermal calculations of an integrated circuit device are reported. The methods may comprise determining a power consumption by a power entity of an integrated circuit, the power entity comprising at least one functional element of the integrated circuit; determining a temperature of a thermal entity, the thermal entity comprising a subset of the power entity; and adjusting at least one of a voltage or an operating frequency of at least one functional element of the power entity, based upon the temperature of the thermal entity being greater than or equal to a predetermined threshold temperature for the thermal entity.

Abstract translation: 报告了与集成电路装置的热计算相关的方法，装置和制造过程。 所述方法可以包括确定集成电路的功率实体的功率消耗，所述功率实体包括所述集成电路的至少一个功能元件; 确定热实体的温度，所述热实体包括所述功率实体的子集; 以及基于所述热实体的温度大于或等于所述热实体的预定阈值温度来调节所述功率实体的至少一个功能元件的电压或工作频率中的至少一个。

公开(公告)号：US20140223199A1

公开(公告)日：2014-08-07

申请号：US13759611

申请日：2013-02-05

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Samuel Naffziger

IPC: G06F1/26

CPC classification number: G06F1/3206 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

Abstract: Methods, apparatus, and fabrication processes relating to thermal calculations of an integrated circuit device are reported. The methods may comprise determining a power consumption by a power entity of an integrated circuit, the power entity comprising at least one functional element of the integrated circuit; determining a temperature of a thermal entity, the thermal entity comprising a subset of the power entity; and adjusting at least one of a voltage or an operating frequency of at least one functional element of the power entity, based upon the temperature of the thermal entity being greater than or equal to a predetermined threshold temperature for the thermal entity.

Abstract translation: 报告了与集成电路装置的热计算相关的方法，装置和制造过程。 所述方法可以包括确定集成电路的功率实体的功率消耗，所述功率实体包括所述集成电路的至少一个功能元件; 确定热实体的温度，所述热实体包括所述功率实体的子集; 以及基于所述热实体的温度大于或等于所述热实体的预定阈值温度来调节所述功率实体的至少一个功能元件的电压或工作频率中的至少一个。

公开(公告)号：US20250117352A1

公开(公告)日：2025-04-10

申请号：US18910202

申请日：2024-10-09

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Alan D. Smith ,  Michael Mantor ,  Mark Fowler ,  Vydhyanathan Kalyanasundharam ,  Samuel Naffziger

IPC: G06F13/40 ,  G06F9/50 ,  G06F12/0893

Abstract: A processing system includes one or more accelerator units (AUs) each having a modular architecture. To this end, each AU includes a connection circuitry and one or more memory stacks disposed on the connection circuitry. Further, each AU includes one or more interposer dies each disposed on the connection circuitry such that each interposer die of the one or more interposer dies is communicatively coupled to a corresponding memory stack of the memory stacks via the connection circuitry. Further, each interposer die of each AU includes circuitry configured to concurrently support two or more types of compute dies.

公开(公告)号：US12266585B2

公开(公告)日：2025-04-01

申请号：US17516988

申请日：2021-11-02

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： John Wuu ,  Samuel Naffziger ,  Patrick J. Shyvers ,  Milind S. Bhagavat ,  Kaushik Mysore ,  Brett P. Wilkerson

IPC: H01L23/367 ,  H01L23/36 ,  H01L25/00 ,  H01L25/065 ,  H01L23/373

Abstract: Various semiconductor chip devices with stacked chips are disclosed. In one aspect, a semiconductor chip device is provided. The semiconductor chip device includes a first semiconductor chip that has a floor plan with a high heat producing area and a low heat producing area. At least one second semiconductor chip is stacked on the low heat producing area. The semiconductor chip device also includes means for transferring heat from the high heat producing area.