公开(公告)号：US20110164016A1

公开(公告)日：2011-07-07

申请号：US12869721

申请日：2010-08-26

Applicant: Chul-Kyu Kang ,  Bo-Yong Chung

Inventor： Chul-Kyu Kang ,  Bo-Yong Chung

IPC: G09G3/32 ,  G06F3/038

CPC classification number: G09G3/3233 ,  G09G2300/0819 ,  G09G2300/0852 ,  G09G2300/0861 ,  G09G2320/0223 ,  G09G2320/043

Abstract: A pixel circuit includes: an OLED; a second transistor including gate, first, and second terminals coupled to a first scan line, a data line, and a first node, respectively; a fourth transistor including gate, first, and second terminals coupled to a third scan line, the first node, and a second node, respectively; a third transistor including gate, first, and second terminals coupled to a second scan line, a reference power source, and the second node, respectively; a fifth transistor including gate, first, and second terminals coupled to a light emission control line, a third node, and an anode of the OLED, respectively; a first capacitor coupled between the first and second nodes; a second capacitor coupled between the second and third nodes; and a first transistor including gate, first, and second terminals coupled to the first node, a first power source, and the third node, respectively.

Abstract translation: 像素电路包括：OLED; 第二晶体管，其分别包括耦合到第一扫描线，数据线和第一节点的栅极，第一和第二端子; 第四晶体管，其分别包括耦合到第三扫描线的栅极，第一和第二端子，所述第一节点和第二节点; 第三晶体管，分别包括耦合到第二扫描线的栅极，第一和第二端子，参考电源和第二节点; 第五晶体管，其分别包括耦合到所述OLED的发光控制线，第三节点和阳极的栅极，第一和第二端子; 耦合在第一和第二节点之间的第一电容器; 耦合在第二和第三节点之间的第二电容器; 以及第一晶体管，其分别包括耦合到所述第一节点的栅极，第一和第二端子，第一电源和所述第三节点。

公开(公告)号：US20110084947A1

公开(公告)日：2011-04-14

申请号：US12832952

申请日：2010-07-08

Applicant: Bo-Yong Chung ,  Keum-Nam Kim

Inventor： Bo-Yong Chung ,  Keum-Nam Kim

IPC: G09G3/32 ,  G09G5/00

CPC classification number: G09G3/3233 ,  G09G2300/0852 ,  G09G2300/0861 ,  G09G2310/0251 ,  G09G2310/0262 ,  G09G2320/043

Abstract: Pixel circuits and an organic electroluminescent display including the same are provided. The pixel circuit includes: an organic light emitting diode; a fifth transistor coupled to a third scan line, a reference power source, and a first node; a first capacitor coupled between the first node and a second node; a second capacitor coupled between the first node and the organic light emitting diode; a fourth transistor coupled to a second scan line, a data line, and the first node; a sixth transistor coupled to a first scan line, a first power source, and the second node; a second transistor coupled to the second scan line, the second node, and a third node; a third transistor coupled to an emission control line, the first power source, and the third node; and a first transistor coupled to the second node, the third node, and the organic light emitting diode.

Abstract translation: 提供像素电路和包括其的有机电致发光显示器。 像素电路包括：有机发光二极管; 耦合到第三扫描线的第五晶体管，参考电源和第一节点; 耦合在所述第一节点和第二节点之间的第一电容器; 耦合在所述第一节点和所述有机发光二极管之间的第二电容器; 耦合到第二扫描线的第四晶体管，数据线和所述第一节点; 耦合到第一扫描线的第六晶体管，第一电源和第二节点; 耦合到第二扫描线的第二晶体管，第二节点和第三节点; 耦合到发射控制线，第一电源和第三节点的第三晶体管; 以及耦合到第二节点，第三节点和有机发光二极管的第一晶体管。

公开(公告)号：US07916601B2

公开(公告)日：2011-03-29

申请号：US12285564

申请日：2008-10-08

Applicant: Joo-youp Kim ,  Seung-bum Lee ,  Jong-hoon Lee ,  Sung-yong Chung

Inventor： Joo-youp Kim ,  Seung-bum Lee ,  Jong-hoon Lee ,  Sung-yong Chung

IPC: G11B7/00

CPC classification number: G11B20/10481 ,  G11B7/0062 ,  G11B7/1267 ,  G11B20/10009

Abstract: A write strategy method, medium, and apparatus. The method includes writing a signal to a storage medium by using a predetermined power and an initial write strategy, calculating variation characteristics of a data signal which separately correspond to variations of write strategy parameters, if the written signal does not satisfy initial quality standards, and calculating correlations among periods of the data signal and correlations among the write strategy parameters by using the variation characteristics of the data signal, and determining the write strategy parameters based on the correlations among the periods of the data signal and the correlations among the write strategy parameters.

Abstract translation: 写策略方法，媒体和装置。 该方法包括：如果写入信号不满足初始质量标准，则通过使用预定功率和初始写入策略将信号写入存储介质，计算分别对应于写入策略参数的变化的数据信号的变化特性，以及 通过使用数据信号的变化特性来计算数据信号的周期和写入策略参数之间的相关性，并且基于数据信号的周期与写入策略参数之间的相关性之间的相关性来确定写入策略参数 。

公开(公告)号：US20110069058A1

公开(公告)日：2011-03-24

申请号：US12730854

申请日：2010-03-24

Applicant: Bo-Yong Chung ,  Keum-Nam Kim

Inventor： Bo-Yong Chung ,  Keum-Nam Kim

IPC: G09G3/30 ,  G09G5/00

CPC classification number: G09G3/3233 ,  G09G2300/043 ,  G09G2300/0819 ,  G09G2300/0852 ,  G09G2310/0262 ,  G09G2320/045

Abstract: A pixel circuit of a display panel, a method of driving the pixel circuit, and an organic light emitting display device including the display panel are provided. All of a plurality of transistors used in the pixel circuit are NMOS transistors, and the pixel circuit is configured to compensate for a voltage change at a source electrode of a driving transistor during light emission.

Abstract translation: 提供了显示面板的像素电路，驱动像素电路的方法以及包括显示面板的有机发光显示装置。 在像素电路中使用的多个晶体管全部是NMOS晶体管，并且像素电路被配置为补偿在发光期间驱动晶体管的源电极处的电压变化。

公开(公告)号：US20100319724A1

公开(公告)日：2010-12-23

申请号：US12457735

申请日：2009-06-19

Applicant: In-Yong CHUNG

Inventor： In-Yong CHUNG

IPC: A45D33/22 ,  A45D40/24

CPC classification number: A45D40/24 ,  A45D33/20 ,  A45D33/22

Abstract: The cosmetics container of the present invention is provided with a casing, pivoting trays and a housing tray that are pivoted into and out of the casing. The casing consists of a top plate and a bottom plate of frame shape, and a side plate arranged vertically between the top plate and bottom plate, and part of the side plate is open. Plural pivoting trays are arranged in a stack between the top plate and bottom plate, and they are drawn in or out through the opening of the casing. At least one of the pivoting trays is a housing tray, in which a housing space is formed for make-up tools. Therefore, the present invention may house cosmetics together with make-up tools, so the portability of cosmetics and make-up tools is improved.

Abstract translation: 本发明的化妆品容器设置有壳体，枢转托盘和壳体托架，该壳体枢转进出壳体。 壳体由顶板和框架底板构成，侧板垂直设置在顶板和底板之间，侧板的一部分是敞开的。 多个枢转托盘在顶板和底板之间堆叠地布置，并且它们通过壳体的开口被拉入或滑出。 枢转托盘中的至少一个是壳体托盘，其中形成用于化妆工具的容纳空间。 因此，本发明可以与化妆工具一起容纳化妆品，从而提高了化妆品和化妆工具的便携性。

公开(公告)号：US07852309B2

公开(公告)日：2010-12-14

申请号：US11490755

申请日：2006-07-20

Applicant: Bo-Yong Chung

Inventor： Bo-Yong Chung

IPC: G09G3/36 ,  G11C19/00 ,  H03K19/20

CPC classification number: G09G3/3266 ,  G09G2300/0408

Abstract: Provided is a scan driver that supplies a scan signal to an organic light emitting display device (OLED). The scan driver includes transistors of the same conductivity type. To generate individual scan signals, the scan driver includes samplers, each of which samples an input signal in synchronization with a clock signal or an inverted clock signal; and an OR gate and a NAND gate, each of which performs a logical operation on output signals of adjacent samplers and generates a scan signal. The samplers, the OR gate and the NOR gate include transistors of the same conductivity type.

Abstract translation: 提供了向有机发光显示装置（OLED）提供扫描信号的扫描驱动器。 扫描驱动器包括相同导电类型的晶体管。 为了产生单独的扫描信号，扫描驱动器包括采样器，每个采样器与时钟信号或反相时钟信号同步地采样输入信号; 以及OR门和NAND门，其中每一个对相邻取样器的输出信号执行逻辑运算并产生扫描信号。 采样器，OR门和NOR门包括相同导电类型的晶体管。

公开(公告)号：US20100208527A1

公开(公告)日：2010-08-19

申请号：US12773232

申请日：2010-05-04

Applicant: Gulzar Ahmed Kathawala ,  Wei Zheng ,  Zhizheng Liu ,  Sung-Yong Chung ,  Timothy Thurgate ,  Kuo-Tung Chang ,  Sheung-Hee Park ,  Gabrielle Wing Han Leung

Inventor： Gulzar Ahmed Kathawala ,  Wei Zheng ,  Zhizheng Liu ,  Sung-Yong Chung ,  Timothy Thurgate ,  Kuo-Tung Chang ,  Sheung-Hee Park ,  Gabrielle Wing Han Leung

IPC: G11C16/04

CPC classification number: G11C16/3418

Abstract: A memory device comprising an optimization component that facilitates erasing memory cells in a substantially homogeneous electromagnetic field and methods that facilitate erasing memory cells in a substantially homogeneous electromagnetic field are presented. The optimization component facilitates selecting a subset of memory cells to be erased at the same time, such that a memory cell in the subset of memory cells has two neighbor memory cells adjacent thereto that are in the subset of memory, or one neighbor memory cell adjacent thereto when the memory cell is an end-row memory cell. The optimization component facilitates performing a Fowler-Nordheim channel erase to erase the subset of memory cells, and a predetermined voltage potential associated with an erase command is applied to each cell of the subset of memory cells to facilitate reducing fringing effect associated with the electromagnetic fields applied to the cells during the erase.

Abstract translation: 提供了一种存储器件，其包括便于擦除基本上均匀的电磁场中的存储器单元的优化部件，以及便于在基本均匀的电磁场中擦除存储器单元的方法。 优化组件有助于同时选择要擦除的存储器单元的子集，使得存储器单元子集中的存储单元具有与存储单元相邻的两个相邻存储器单元，其位于存储器的子集中，或者相邻的一个相邻存储器单元 当存储器单元是端行存储单元时。 优化组件有助于执行Fowler-Nordheim信道擦除来擦除存储器单元的子集，并且与擦除命令相关联的预定电压电位被施加到存储器单元子集的每个单元，以便于减少与电磁场相关联的边缘效应 在擦除期间应用于细胞。

公开(公告)号：US07746698B2

公开(公告)日：2010-06-29

申请号：US11956032

申请日：2007-12-13

Applicant: Zhizheng Liu ,  An Chen ,  Wei Zheng ,  Kuo-Tung Chang ,  Sung-Yong Chung ,  Gulzar Ahmed Kathawala ,  Ashot Melik-Martirosian

Inventor： Zhizheng Liu ,  An Chen ,  Wei Zheng ,  Kuo-Tung Chang ,  Sung-Yong Chung ,  Gulzar Ahmed Kathawala ,  Ashot Melik-Martirosian

IPC: G11C16/04

CPC classification number: G11C16/0491 ,  G11C16/12

Abstract: Systems and methods that facilitate improved programming memory cells in a nonvolatile memory (e.g., flash memory) are presented. An optimized voltage component can facilitate supplying respective voltages to a source, drain, and gate associated with a memory cell during operations, such as programming operations. The optimized voltage component can facilitate supplying a predetermined source bitline voltage to a memory cell during programming of the cell to facilitate reducing leakage currents associated with the bitlines, which can improve programming of the memory cell, and to facilitate reducing the programming current, which can result in power efficient programming and improved programming speed.

Abstract translation: 提出了有助于改进非易失性存储器（例如闪速存储器）中的编程存储器单元的系统和方法。 优化的电压分量可以有助于在诸如编程操作的操作期间向与存储器单元相关联的源极，漏极和栅极提供相应的电压。 优化的电压分量可以有助于在单元的编程期间向存储器单元提供预定的源位线电压，以便于减少与位线相关联的泄漏电流，这可以改善存储器单元的编程，并且有助于减少编程电流， 导致功率有效的编程和改进的编程速度。

公开(公告)号：US20100128521A1

公开(公告)日：2010-05-27

申请号：US12275663

申请日：2008-11-21

Applicant: Yuji Mizuguchi ,  Mark W. Randolph ,  Darlene Gay Hamilton ,  Yi He ,  Zhizheng Liu ,  Yanxia (Emma) Lin ,  Xianmin Yi ,  Gulzar Kathawala ,  Amol Ramesh Joshi ,  Kuo-Tung Chang ,  Edward Franklin Runnion ,  Sung-Chul Lee ,  Sung-Yong Chung ,  Yanxiang Liu ,  Yu Sun

Inventor： Yuji Mizuguchi ,  Mark W. Randolph ,  Darlene Gay Hamilton ,  Yi He ,  Zhizheng Liu ,  Yanxia (Emma) Lin ,  Xianmin Yi ,  Gulzar Kathawala ,  Amol Ramesh Joshi ,  Kuo-Tung Chang ,  Edward Franklin Runnion ,  Sung-Chul Lee ,  Sung-Yong Chung ,  Yanxiang Liu ,  Yu Sun

IPC: G11C16/04

CPC classification number: G11C16/26 ,  G11C16/08 ,  G11C16/3427

Abstract: Systems, methods, and devices that facilitate applying a predefined negative gate voltage to wordlines adjacent to a selected wordline associated with a memory cell selected during a read or verify operation to facilitate reducing adjacent wordline disturb are presented. A memory component can comprise an optimized operation component that can apply a predefined negative gate voltage to wordlines adjacent to a selected wordline associated with a memory cell selected for a read or verify operation, based at least in part on predefined operation criteria, to facilitate reducing adjacent wordline disturb in the selected memory cell to facilitate reducing a shift in the voltage threshold and maintain a desired operation window. The optimized operation component optionally can include an evaluator component that can facilitate determining whether a negative gate voltage applied to adjacent wordlines is to be adjusted to facilitate reducing adjacent wordline disturb below a predetermined threshold amount.

Abstract translation: 提出了有助于将预定义的负栅极电压施加到与在读取或验证操作期间选择的存储器单元相关联的所选字线相邻的字线的系统，方法和设备，以便于减少相邻字线干扰。 存储器组件可以包括优化的操作部件，其可以至少部分地基于预定义的操作标准，将预定义的负栅极电压施加到与被选择用于读取或验证操作所选择的存储器单元相关联的所选字线相邻的字线上，以便减少 所选择的存储单元中的相邻字线干扰，以便减少电压阈值的移位并保持期望的操作窗口。 优化的操作组件可选地可以包括评估器组件，其可以便于确定施加到相邻字线的负栅极电压是否被调整以便于将相邻字线干扰降低到低于预定阈值量。

公开(公告)号：US07679967B2

公开(公告)日：2010-03-16

申请号：US11963508

申请日：2007-12-21

Applicant: Sung-Yong Chung ,  Zhizheng Liu ,  Yugi Mizuguchi ,  Xuguang Alan Wang ,  Yi He ,  Ming Kwan ,  Darlene Hamilton ,  Sung-Chul Lee ,  Guowei Wang ,  Nancy Leong

Inventor： Sung-Yong Chung ,  Zhizheng Liu ,  Yugi Mizuguchi ,  Xuguang Alan Wang ,  Yi He ,  Ming Kwan ,  Darlene Hamilton ,  Sung-Chul Lee ,  Guowei Wang ,  Nancy Leong

IPC: G11C16/06

CPC classification number: G11C16/3418 ,  G11C16/0416 ,  G11C16/24 ,  G11C16/3427

Abstract: A system and methodology that can minimize disturbance during an AC operation associated with a memory, such as, program, read and/or erase, is provided. The system pre-charges all or a desired subset of the bit lines in a memory array to a specified voltage, during an AC operation to facilitate reducing AC disturbances between neighboring cells. A pre-charge voltage can be applied to all bit lines in a block in the memory array, or to bit lines associated with a selected memory cell and neighbor memory cells adjacent to the selected memory cell in the block. The system ensures that source and drain voltage levels can be set to desired levels at the same or substantially the same time, while selecting a memory cell. This can facilitate minimizing AC disturbances in the selected memory cell during the AC operation.

Abstract translation: 提供了一种能够在与诸如程序，读取和/或擦除之类的存储器相关联的AC操作期间最小化干扰的系统和方法。 在AC操作期间，系统将存储器阵列中的所有或所需的位线子集预充电到指定的电压，以便于减少相邻单元之间的AC干扰。 可以将预充电电压施加到存储器阵列中的块中的所有位线，或者对与所选择的存储器单元相关联的位线以及与块中所选择的存储单元相邻的相邻存储单元。 该系统确保在选择存储器单元时，源极和漏极电压电平可以在相同或基本相同的时间被设置为期望的电平。 这可以有助于在AC操作期间最小化所选择的存储器单元中的AC干扰。