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    Semiconductor memory device operating in synchronization with a clock signal for high-speed data write and data read operations
    21.
    发明授权
    Semiconductor memory device operating in synchronization with a clock signal for high-speed data write and data read operations 有权
    半导体存储器件与时钟信号同步工作，用于高速数据写入和数据读取操作

    公开(公告)号：US06427197B1

    公开(公告)日：2002-07-30

    申请号：US09394891

    申请日：1999-09-13

    Applicant: Yasuharu Sato ,  Tadao Aikawa ,  Shinya Fujioka ,  Waichiro Fujieda ,  Hitoshi Ikeda ,  Hiroyuki Kobayashi

    Inventor： Yasuharu Sato ,  Tadao Aikawa ,  Shinya Fujioka ,  Waichiro Fujieda ,  Hitoshi Ikeda ,  Hiroyuki Kobayashi

    IPC: G11C800

    CPC classification number: G11C7/1072 ,  G11C7/1039

    Abstract: The present invention is a memory circuit for writing prescribed numbers of bits of write data, determined according to the burst length, in response to write command, comprising: a first stage for inputting, and then holding, row addresses and column addresses simultaneously with the write command; a second stage having a memory core connected to the first stage via a pipeline switch, wherein the row addresses and column addresses are decoded, and word line and sense amps are activated; a third stage for inputting the write data serially and sending the write data to the memory core in parallel; and a serial data detection circuit for generating write-pipeline control signal for making the pipeline switch conduct, after the prescribed number of bits of write data has been inputted. According to the present invention, in an FCRAM exhibiting a pipeline structure, the memory core in the second stage can be activated after safely fetching the write data in the burst length. When writing successively or reading successively, moreover, the command cycle can made short irrespective of the burst length.

    Abstract translation: 本发明是一种存储电路，用于响应于写命令，写入根据突发长度确定的指定数量的写入数据，包括：第一级，用于与第一级同时输入，然后保持行地址和列地址 写命令 第二级具有经由流水线开关连接到第一级的存储器核，其中行地址和列地址被解码，字线和检测放大器被激活; 用于串行输入写入数据并且将写入数据并行地发送到存储器核心的第三级; 以及串行数据检测电路，用于在输入了规定数量的写入数据之后，产生用于使流水线开关导通的写入流水线控制信号。 根据本发明，在呈现流水线结构的FCRAM中，可以在以突发长度安全地取出写入数据之后激活第二级中的存储器核心。 此外，当连续写入或连续读取时，无论突发长度如何，命令循环可以变短。

    Memory device with a plurality of common data buses
    22.
    发明授权
    Memory device with a plurality of common data buses 有权
    具有多个公共数据总线的存储器件

    公开(公告)号：US06333890B1

    公开(公告)日：2001-12-25

    申请号：US09695302

    申请日：2000-10-25

    Applicant: Masahiro Niimi ,  Shinya Fujioka ,  Tadao Aikawa ,  Yasuharu Sato

    Inventor： Masahiro Niimi ,  Shinya Fujioka ,  Tadao Aikawa ,  Yasuharu Sato

    IPC: G11C800

    CPC classification number: G11C7/106 ,  G11C7/1006 ,  G11C7/1051 ,  G11C7/1069 ,  G11C7/18 ,  G11C8/12 ,  G11C2207/108

    Abstract: According to an aspect of the present invention, a memory device having a plurality of banks carries out bank interleaving by use of a plurality of common data buses, the number of which is less than the number of the banks. The present invention enables the data to be read more rapidly while suppressing the increase of the chip area. According to the present invention, there is provided a memory device having a plurality of banks each including a plurality of memory cells, and reading or writing data from or into the memory cells in synchronism with a clock signal, the memory device comprising: a sense amplifier disposed on each of the plurality of banks, for amplifying data read from the memory cells; a plurality of common data buses shared by the plurality of banks, the number of the common data buses being less than the number of the banks; and a switching circuit disposed on each of the plurality of banks, for feeding or receiving data of the each bank to or from the plurality of common data buses; wherein read or write of data of the plurality of banks is made through successive selection of the plurality of common data buses by the switching circuit.

    Abstract translation: 根据本发明的一个方面，具有多个存储体的存储器件通过使用多个公共数据总线执行存储体交织，该数据总线的数量少于存储体的数量。 本发明能够在抑制芯片面积的增加的同时更快地读取数据。 根据本发明，提供了一种具有多个存储单元的存储器件，每个存储单元包括多个存储器单元，以及与时钟信号同步地从存储器单元读取或写入数据，所述存储器件包括：感测 放大器设置在所述多个存储体中的每一个上，用于放大从所述存储器单元读取的数据; 由所述多个银行共享的多个公用数据总线，所述公共数据总线的数量小于所述存储体的数量; 以及切换电路，其设置在所述多个存储体中的每一个上，用于向所述多个公共数据总线馈送或接收每个存储体的数据; 其中通过所述切换电路连续选择所述多个公用数据总线来进行所述多个存储体的数据的读取或写入。

    Bit line reset circuit of memory
    23.
    发明授权
    Bit line reset circuit of memory 失效
    存储器的位线复位电路

    公开(公告)号：US6026034A

    公开(公告)日：2000-02-15

    申请号：US73928

    申请日：1998-05-07

    Applicant: Takaaki Suzuki ,  Shinya Fujioka ,  Yasuharu Sato

    Inventor： Takaaki Suzuki ,  Shinya Fujioka ,  Yasuharu Sato

    IPC: G11C11/409 ,  G11C7/06 ,  G11C7/12 ,  G11C11/407 ,  G11C11/4091 ,  G11C11/4094 ,  G11C7/00

    CPC classification number: G11C7/065 ,  G11C11/4091 ,  G11C11/4094 ,  G11C7/12

    Abstract: Switching transistors 20, 22, 22P, 21, 23 and 23P and a portion of control circuit for transistors 20 and 21 constitutes a bit line reset circuit on memory cell side. In reading `H` from the memory cell connected to a bit line BLC or *BLC, the both bit lines are set at a higher reset potential Vii, while in reading `L`, the both bit lines are reset at a lower reset potential Vss. Transfer gates 10 and 11 are turned off before sufficient amplification of a potential difference between the bit lines BL and *BL. The operation of restoring into a memory cell read destructively from is performed in parallel with the operation of bit line reset.

    Abstract translation: 开关晶体管20,22,22P，21,23和23P以及用于晶体管20和21的控制电路的一部分构成存储单元侧的位线复位电路。 在从连接到位线BLC或* BLC的存储单元读取“H”时，两个位线都被设置在较高的复位电位Vii，而在读取“L”时，两个位线都以较低的复位电位复位 Vss。 在充分放大位线BL和* BL之间的电位差之前，转移门10和11被截止。 与位线复位的操作并行执行从存储单元中恢复读取的操作。

    Semiconductor memory including program circuit of nonvolatile memory cells and system
    26.
    发明授权
    Semiconductor memory including program circuit of nonvolatile memory cells and system 有权
    半导体存储器包括非易失性存储单元和系统的程序电路

    公开(公告)号：US08514632B2

    公开(公告)日：2013-08-20

    申请号：US13022410

    申请日：2011-02-07

    Applicant: Motoi Takahashi ,  Yasuharu Sato

    Inventor： Motoi Takahashi ,  Yasuharu Sato

    IPC: G11C16/06

    CPC classification number: G11C16/0433 ,  G11C16/08 ,  G11C16/10

    Abstract: A semiconductor memory includes a plurality of nonvolatile memory cells arranged in a matrix and coupled to control gate lines, selection gate lines, bit lines, and source lines, and includes a source line control unit. The source line control unit, at a time of program operation, sets one of the source lines coupled to a row of the memory cells including a program memory cell to a high level voltage, and sets at least one of the remaining source lines coupled to a row of a non-program memory cells to be higher than a low level voltage of the selection gate lines and to be lower than the high level voltage of an unselection bit line. Thereby, a leak current lowering a voltage of the source lines at the time of program operation can be blocked off, and a program operation time may be shortened.

    Abstract translation: 半导体存储器包括以矩阵方式布置并耦合到控制栅极线，选择栅极线，位线和源极线的多个非易失性存储器单元，并且包括源极线控制单元。 源极线控制单元在编程操作时，将耦合到包括程序存储单元的存储单元的一行的源极线之一设置为高电平电压，并且将至少一个剩余的源极线耦合到 非编程存储单元的一行高于选择栅极线的低电平电压并且低于非选择位线的高电平电压。 因此，可以阻止在编程操作时降低源极线的电压的漏电流，并且可以缩短编程操作时间。

    Semiconductor integrated circuit device
    28.
    发明授权
    Semiconductor integrated circuit device 有权
    半导体集成电路器件

    公开(公告)号：US06789209B1

    公开(公告)日：2004-09-07

    申请号：US09615952

    申请日：2000-07-13

    Applicant: Takaaki Suzuki ,  Yasuharu Sato

    Inventor： Takaaki Suzuki ,  Yasuharu Sato

    IPC: G06F104

    CPC classification number: G11C7/1066 ,  G11C7/1051 ,  G11C7/1087 ,  G11C7/22 ,  G11C7/222

    Abstract: In a semiconductor integrated circuit device operating in synchronism with a clock supplied from the outside of the device, there is provided a circuit generating, from the clock, an output strobe signal for outputting data from the device and outputting the output strobe signal to the outside of the device.

    Abstract translation: 在与从器件外部提供的时钟同步工作的半导体集成电路器件中，提供从时钟产生用于从器件输出数据并将输出选通信号输出到外部的输出选通信号的电路 的设备。

    Semiconductor memory circuit having selective redundant memory cells
    29.
    发明授权
    Semiconductor memory circuit having selective redundant memory cells 有权
    具有选择性冗余存储单元的半导体存储器电路

    公开(公告)号：US06496430B2

    公开(公告)日：2002-12-17

    申请号：US10131221

    申请日：2002-04-25

    Applicant: Tadao Aikawa ,  Takaaki Suzuki ,  Yasuharu Sato ,  Hiroyuki Kobayashi

    Inventor： Tadao Aikawa ,  Takaaki Suzuki ,  Yasuharu Sato ,  Hiroyuki Kobayashi

    IPC: G11C2900

    CPC classification number: G11C29/808

    Abstract: A semiconductor memory circuit includes a plurality of memory cell arrays arranged in rows and columns. A decoder circuit selects a predetermined number of memory cell arrays from among the plurality of the memory cell arrays. Sense amplifiers sense data read from selected memory cell arrays. The plurality of memory cell arrays are grouped into a first type of memory cell arrays each having a redundant memory cell and a second type of memory cell arrays each having no redundant memory cell.

    Abstract translation: 半导体存储器电路包括以行和列排列的多个存储单元阵列。 解码器电路从多个存储单元阵列中选择预定数量的存储单元阵列。 感测放大器感测从选定的存储单元阵列读取的数据。 多个存储单元阵列被分组成第一类型的存储单元阵列，每个存储单元阵列具有冗余存储单元和每个不具有冗余存储单元的第二类型存储单元阵列。

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