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21.发明授权公开(公告)号：US12256156B2
公开(公告)日：2025-03-18
申请号：US17940742
申请日：2022-09-08
Applicant: STMicroelectronics France
Inventor： Pol Perrin
IPC: H04N23/84 , G06T3/4015 , H04N9/64 , H04N23/10 , H04N23/11 , H04N25/131
Abstract: The method for processing a matrix of pixels each containing an original red, green, blue, or infrared component, comprises at least one interpolation of an interpolated component different from the original component of a pixel of interest from the components of a group of pixels neighboring the pixel of interest. The interpolation comprises: a calculation of the sum of the components of reference pixels weighted by a respectively assigned weight, the reference pixels being pixels of the group having the same original component as the interpolated component, an evaluation of the spatial uniformity of an environment, within the group of each reference pixel, a calculation of the weights assigned to the reference pixels at values which are normalized and proportional to the respective spatial uniformity.
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公开(公告)号：US12192652B2
公开(公告)日：2025-01-07
申请号：US18482117
申请日：2023-10-06
Applicant: STMicroelectronics France
Inventor： Valentin Rebiere , Antoine Drouot
IPC: H04N25/60 , H04N23/84 , H04N25/13 , H04N25/705
Abstract: An embodiment method for estimating a missing or incorrect value in a table of values generated by a photosite matrix comprises a definition of a zone of the table comprising the value to be estimated and other values, referred to as neighboring values, and an estimation of the value to be estimated based on the primary neighboring values and the weight associated with these primary neighboring values, wherein a weight of each neighboring value, referred to as primary neighboring value, of the same colorimetric component as that of the missing or incorrect value to be estimated, is determined according to differences between neighboring values disposed on an axis and neighboring values disposed parallel with this axis and positioned in relation to this axis on the same side as the primary neighboring value for which the weight is determined.
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公开(公告)号：US12164316B2
公开(公告)日：2024-12-10
申请号：US18119535
申请日：2023-03-09
Applicant: STMicroelectronics (Rousset) SAS , STMicroelectronics France , STMicroelectronics (Alps) SAS
Inventor： Alexandre Tramoni , Florent Sibille , Patrick Arnould
Abstract: An electronic device includes a near-field communication module and a powering circuit for delivering a power supply voltage to the near-field communication module. When the near-field communication module is in a low power mode, the powering circuit is configured for an operational mode where it is periodically started to provide the power supply voltage.
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24.发明授权公开(公告)号：US12141590B2
公开(公告)日：2024-11-12
申请号：US17898306
申请日：2022-08-29
Inventor： Frederic Ruelle , Emmanuel Grandin , Bechir Jabri
IPC: G06F9/445 , G06F3/0482 , G06F9/4401 , G06F9/451
Abstract: System, method, and circuitry for generating content for a programmable computing device based on user-selected configuration information. A settings registry is generated based on the user's selections. The settings registry and the user selected configuration information is utilized to generate the content, such as code, data, parameters, settings, etc. When the content is provided to the programmable computing device, the content initializes, configures, or controls one or more software and hardware aspects of the programmable computing device, such as boot sequence configurations, internal peripheral configurations, states of the programmable computing device, transitions between states of the programmable computing device, etc., and various combinations thereof.
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公开(公告)号：US12039092B2
公开(公告)日：2024-07-16
申请号：US17544038
申请日：2021-12-07
Applicant: STMicroelectronics France , STMicroelectronics (Alps) SAS
Inventor： Julien Goulier , Pascal Bernon
CPC classification number: G06F21/755 , H03K3/037 , H03K3/84
Abstract: The present description concerns an integrated circuit including, between first and second terminals having a first voltage applied therebetween, a load configured to execute instructions, a circuit for delivering a digital signal having at least two bits from a binary signal and a current output digital-to-analog converter controlled by the digital signal and coupled between the first and second terminals in parallel with the load.
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Patent Agency Ranking
公开(公告)号：US20240235907A9
公开(公告)日：2024-07-11
申请号：US18491212
申请日：2023-10-20
Applicant: STMicroelectronics France
Inventor： Florence Giry-Cassan
IPC: H04L27/227 , H03B5/12
CPC classification number: H04L27/2273 , H03B5/1228 , H03B2200/0078
Abstract: Embodiments provide a device that includes a first circuit having a first input to receive a first sine wave signal and a second input to receive a second sine wave signal in quadrature with respect to each other and a current mode logic gate having a first input coupled to a first output of the first circuit and a second input coupled to a second output of the first circuit. The first circuit configured to deliver a first square wave signal and a second square wave signal. The current mode logic gate is configured to deliver a third square wave signal at a first level and a fourth square wave signal at a second level when the first and second square wave signals are simultaneously at their first levels and the first square wave signal is ahead of the second square wave signal.
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公开(公告)号：US20240105730A1
公开(公告)日：2024-03-28
申请号：US18532984
申请日：2023-12-07
Inventor： Olivier WEBER , Christophe LECOCQ
IPC: H01L27/12 , H01L21/8238 , H01L21/84 , H01L27/02 , H01L27/092
CPC classification number: H01L27/1203 , H01L21/823807 , H01L21/84 , H01L27/0207 , H01L27/092
Abstract: An integrated circuit includes at least a first standard cell framed by two second standard cells. The three cells are disposed adjacent to each other, and each standard cell includes at least one NMOS transistor and at least one least one PMOS transistor located in and on a silicon-on-insulator substrate. The at least one PMOS transistor of the first standard cell has a channel including silicon and germanium. The at least one PMOS transistor of each second standard cell has a silicon channel and a threshold voltage different in absolute value from the threshold voltage of said at least one PMOS transistor of the first cell.
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28.发明授权公开(公告)号：US12270842B2
公开(公告)日：2025-04-08
申请号：US17421801
申请日：2019-01-22
Applicant: CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE , STMicroelectronics France , UNIVERSITE DE BORDEAUX , INSTITUT POLYTECHNIQUE DE BORDEAUX
Inventor： Vincent Knopik , Jeremie Forest , Eric Kerherve
Abstract: In an embodiment method for detecting the phase of an analog signal via a hybrid coupler operating in a power-combiner mode, the hybrid coupler comprises a first input intended to receive the analog signal, a second input intended to receive a reference signal having a reference phase and the same frequency as the analog signal, and two outputs, and is configured to generate, at these two outputs, a first output signal and a second output signal, respectively. The embodiment method comprises measuring peak values of the analog signal, of the reference signal, and of at least one of the first and second output signals, calculating the phase shift between the phase of the analog signal and the reference phase depending on the measured peak values, and determining the phase of the analog signal depending on the calculated phase shift and the reference phase.
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公开(公告)号：US20240201383A1
公开(公告)日：2024-06-20
申请号：US18538800
申请日：2023-12-13
Inventor： Brent Edward Hearn , Thierry Lebihen , Olivier Pothier
IPC: G01S17/894 , G01B11/22 , G01S7/481 , G01S7/4865
CPC classification number: G01S17/894 , G01B11/22 , G01S7/4816 , G01S7/4865
Abstract: A method includes estimating first distance values associated with a plurality of first pixels, based on light pulses of a first light pulse train having a first period, estimating second distance values associated with a plurality of second pixels, the second distance values being estimated for each second pixel based on a second light pulse train having a second period different from the first period, for each of the first pixels being adjacent to one of the second pixels, validating or invalidating the first distance values, based on a comparison between the estimations of the first distance value and at least one of the second distance values of at least one second adjacent pixel, and storing an indication of the first pixels having been validated and/or invalidated.
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公开(公告)号：US20240137254A1
公开(公告)日：2024-04-25
申请号：US18491212
申请日：2023-10-19
Applicant: STMicroelectronics France
Inventor： Florence Giry-Cassan
IPC: H04L27/227 , H03B5/12
CPC classification number: H04L27/2273 , H03B5/1228 , H03B2200/0078
Abstract: Embodiments provide a device that includes a first circuit having a first input to receive a first sine wave signal and a second input to receive a second sine wave signal in quadrature with respect to each other and a current mode logic gate having a first input coupled to a first output of the first circuit and a second input coupled to a second output of the first circuit. The first circuit configured to deliver a first square wave signal and a second square wave signal. The current mode logic gate is configured to deliver a third square wave signal at a first level and a fourth square wave signal at a second level when the first and second square wave signals are simultaneously at their first levels and the first square wave signal is ahead of the second square wave signal.
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