公开(公告)号：US5550089A

公开(公告)日：1996-08-27

申请号：US217332

申请日：1994-03-23

Applicant: Niloy K. Dutta ,  Russell J. Fischer ,  Neil E. J. Hunt ,  Matthias Passlack ,  Erdmann F. Schubert ,  George J. Zydzik

Inventor： Niloy K. Dutta ,  Russell J. Fischer ,  Neil E. J. Hunt ,  Matthias Passlack ,  Erdmann F. Schubert ,  George J. Zydzik

IPC: C23C14/08 ,  H01L29/51 ,  H01L31/04 ,  H01L33/44 ,  H01S5/00 ,  H01S5/028 ,  H01L21/00 ,  H01L21/02 ,  H01L21/302 ,  H01L21/463

CPC classification number: H01L29/517 ,  C23C14/08 ,  H01L33/44 ,  H01S5/028

Abstract: An optoelectronic lII-V or II-VI semiconductor device comprises a thin film coating with optical characteristics providing low midgap interface state density. A field effect device for inversion channel applications on III-V semiconductors also comprises a thin dielectric film providing required interface characteristics. The thin film is also applicable to passivation of states on exposed surfaces of electronic III-V devices. The thin film comprises a uniform, homogeneous, dense, stoichiometric gallium oxide (Ga.sub.2 O.sub.3) dielectric thin film, fabricated by electron-beam evaporation of a single crystal, high purity Gd.sub.3 Ga.sub.5 O.sub.12 complex compound on semiconductor substrates kept at temperatures ranging from 40.degree. to 370.degree. C. and at background pressures at or above 1.times.10.sup.-10 Torr.

Abstract translation: 光电子II-V或II-VI半导体器件包括具有提供低中间界面态密度的光学特性的薄膜涂层。 用于III-V半导体上的反向沟道应用的场效应器件还包括提供所需接口特性的薄电介质膜。 薄膜也适用于电子III-V器件暴露表面的状态钝化。 该薄膜包括均匀，均匀，致密的化学计量的氧化镓（Ga 2 O 3）电介质薄膜，其通过在保持在40℃至370℃的温度范围内的半导体衬底上的单晶，高纯度Gd 3 Ga 5 O 12络合物的电子束蒸发 在背景压力为1×10-10乇或以上。

公开(公告)号：US09209180B2

公开(公告)日：2015-12-08

申请号：US12974954

申请日：2010-12-21

Applicant: Matthias Passlack

Inventor： Matthias Passlack

IPC: H01L29/15 ,  H01L31/0256 ,  H01L27/092 ,  B82Y10/00 ,  H01L29/12 ,  H01L29/205 ,  H01L29/43 ,  H01L29/778 ,  H01L29/20 ,  H01L31/18 ,  H01L31/0352 ,  H01L31/0304 ,  H01L29/201 ,  H01L29/51

CPC classification number: H01L29/7787 ,  B82Y10/00 ,  H01L21/8252 ,  H01L27/088 ,  H01L27/092 ,  H01L29/122 ,  H01L29/155 ,  H01L29/20 ,  H01L29/201 ,  H01L29/205 ,  H01L29/432 ,  H01L29/517 ,  H01L29/7783 ,  H01L31/03046 ,  H01L31/035236 ,  H01L31/1844

Abstract: A uni-terminal transistor device is described. In one embodiment, an n-channel transistor comprises a first semiconductor layer having a discrete hole level H0; a second semiconductor layer having a conduction band minimum EC2; a wide bandgap semiconductor barrier layer disposed between the first and the second semiconductor layers; a gate dielectric layer disposed above the first semiconductor layer; and a gate metal layer disposed above the gate dielectric layer and having an effective workfunction selected to position the discrete hole level H0 below the conduction band minimum Ec2 for zero bias applied to the gate metal layer and to obtain n-terminal characteristics.

Abstract translation: 描述了一个单端晶体管器件。 在一个实施例中，n沟道晶体管包括具有离散孔级H0的第一半导体层; 具有导带最小EC2的第二半导体层; 布置在第一和第二半导体层之间的宽带隙半导体阻挡层; 设置在所述第一半导体层上方的栅介质层; 以及栅极金属层，其设置在所述栅极介电层上方并且具有选择的有效功函数以将所述离散孔电平H0定位在所述导带最小值Ec2以下，以将零偏压施加到所述栅极金属层并获得n端子特性。

公开(公告)号：US08916927B2

公开(公告)日：2014-12-23

申请号：US13553405

申请日：2012-07-19

Applicant: Krishna Bhuwalka ,  Gerben Doornbos ,  Matthias Passlack

Inventor： Krishna Bhuwalka ,  Gerben Doornbos ,  Matthias Passlack

IPC: H01L29/66 ,  H01L21/336

CPC classification number: H01L29/66977 ,  B82Y10/00 ,  H01L29/0657 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/0688 ,  H01L29/1037 ,  H01L29/1054 ,  H01L29/205 ,  H01L29/42372 ,  H01L29/66356 ,  H01L29/66439 ,  H01L29/66522 ,  H01L29/66666 ,  H01L29/7391 ,  H01L29/775 ,  H01L29/7827

Abstract: Among other things, one or more techniques for forming a vertical tunnel field effect transistor (FET), and a resulting vertical tunnel FET are provided herein. In an embodiment, the vertical tunnel FET is formed by forming a core over a first type substrate region, forming a second type channel shell around a circumference greater than a core circumference, forming a gate dielectric around a circumference greater than the core circumference, forming a gate electrode around a circumference greater than the core circumference, and forming a second type region over a portion of the second type channel shell, where the second type has a doping opposite a doping of the first type. In this manner, line tunneling is enabled, thus providing enhanced tunneling efficiency for a vertical tunnel FET.

Abstract translation: 除此之外，本文提供了用于形成垂直隧道场效应晶体管（FET）的一种或多种技术以及所产生的垂直隧道FET。 在一个实施例中，垂直隧道FET通过在第一类型的衬底区域上形成芯体形成，围绕围绕圆周的圆周形成第二类型沟道壳体，围绕围绕圆周的圆周形成栅极电介质，形成 围绕圆周大于芯圆周的栅电极，并且在第二类型沟槽壳体的一部分上形成第二类型区域，其中第二类型具有与第一类型的掺杂相反的掺杂。 以这种方式，能够进行线路隧道，从而为垂直隧道FET提供增强的隧道效率。

公开(公告)号：US08604518B2

公开(公告)日：2013-12-10

申请号：US13307738

申请日：2011-11-30

Applicant: Krishna Kumar Bhuwalka ,  Gerben Doornbos ,  Matthias Passlack

Inventor： Krishna Kumar Bhuwalka ,  Gerben Doornbos ,  Matthias Passlack

IPC: H01L29/66

CPC classification number: H01L29/66431 ,  H01L29/1054 ,  H01L29/205 ,  H01L29/267 ,  H01L29/66522 ,  H01L29/66795 ,  H01L29/785

Abstract: A Fin Field-Effect Transistor (FinFET) includes a fin, which includes a channel splitter having a first bandgap, and a channel including a first portion and a second portion on opposite sidewalls of the channel splitter. The channel has a second bandgap smaller than the first bandgap. A gate electrode includes a first portion and a second portion on opposite sides of the fin. A gate insulator includes a first portion between the first portion of the gate electrode and the first portion of the channel, and a second portion between the second portion of the gate electrode and the second portion of the channel.

Abstract translation: 鳍场效应晶体管（FinFET）包括鳍，其包括具有第一带隙的沟道分离器和包括在沟道分离器的相对侧壁上的第一部分和第二部分的沟道。 通道具有小于第一带隙的第二带隙。 栅极电极包括在鳍片的相对侧上的第一部分和第二部分。 栅极绝缘体包括位于栅极电极的第一部分和沟道的第一部分之间的第一部分，以及栅电极的第二部分和沟道的第二部分之间的第二部分。

公开(公告)号：US08592878B2

公开(公告)日：2013-11-26

申请号：US13042948

申请日：2011-03-08

Applicant: Bruce M. Green ,  Haldane S. Henry ,  Chun-Li Liu ,  Karen E. Moore ,  Matthias Passlack

Inventor： Bruce M. Green ,  Haldane S. Henry ,  Chun-Li Liu ,  Karen E. Moore ,  Matthias Passlack

IPC: H01L29/66

CPC classification number: H01L21/28581 ,  H01L21/28587 ,  H01L29/0657 ,  H01L29/2003 ,  H01L29/42316 ,  H01L29/432 ,  H01L29/475 ,  H01L29/7787

Abstract: Embodiments include semiconductor devices with low leakage Schottky contacts. An embodiment is formed by providing a partially completed semiconductor device including a substrate, a semiconductor on the substrate, and a passivation layer on the semiconductor, and using a first mask, locally etching the passivation layer to expose a portion of the semiconductor. Without removing the first mask, a Schottky contact is formed of a first material on the exposed portion of the semiconductor, and the first mask is removed. Using a further mask, a step-gate conductor of a second material electrically coupled to the Schottky contact is formed overlying parts of the passivation layer adjacent to the Schottky contact. By minimizing the process steps between opening the Schottky contact window in the passivation layer and forming the Schottky contact material in this window, the gate leakage of a resulting field effect device having a Schottky gate may be substantially reduced.

Abstract translation: 实施例包括具有低泄漏肖特基接触的半导体器件。 通过提供部分完成的半导体器件形成一个实施例，该半导体器件包括衬底，衬底上的半导体和半导体上的钝化层，并且使用第一掩模，局部蚀刻钝化层以暴露半导体的一部分。 在不去除第一掩模的情况下，在半导体的暴露部分上由第一材料形成肖特基接触，并且去除第一掩模。 使用另外的掩模，电耦合到肖特基接触的第二材料的阶梯栅导体形成在与肖特基接触相邻的钝化层的部分上。 通过最小化打开钝化层中的肖特基接触窗口并在该窗口中形成肖特基接触材料之间的工艺步骤，可以显着减少所得到的具有肖特基栅极的场效应器件的栅极泄漏。

公开(公告)号：US20110193091A1

公开(公告)日：2011-08-11

申请号：US12974775

申请日：2010-12-21

Applicant: Matthias Passlack

Inventor： Matthias Passlack

IPC: H01L29/12

CPC classification number: H01L29/7783 ,  H01L21/823807 ,  H01L21/8252 ,  H01L27/0605 ,  H01L27/092 ,  H01L29/517 ,  H01L29/7781

Abstract: Layer structures for use in density of states (“DOS”) engineered FETs are described. One embodiment comprises a layer structure for use in fabricating an n-channel transistor. The layer structure includes a first semiconductor layer having a conduction band minimum EC1; a second semiconductor layer having a discrete hole level H0; a wide bandgap semiconductor barrier layer disposed between the first and the second semiconductor layers; a gate dielectric layer disposed above the first semiconductor layer; and a gate metal layer disposed above the gate dielectric layer; wherein the discrete hole level H0 is positioned below the conduction band minimum Ec1 for zero bias applied to the gate metal layer.

Abstract translation: 描述了用于状态密度（“DOS”）工程化FET的层结构。 一个实施例包括用于制造n沟道晶体管的层结构。 层结构包括具有导带最小EC1的第一半导体层; 具有离散孔级H0的第二半导体层; 布置在第一和第二半导体层之间的宽带隙半导体阻挡层; 设置在所述第一半导体层上方的栅介质层; 以及栅极金属层，其设置在所述栅极介电层上方; 其中离散孔电平H0位于施加到栅极金属层的零偏压的导带最小值Ec1之下。

公开(公告)号：US07799647B2

公开(公告)日：2010-09-21

申请号：US11831394

申请日：2007-07-31

Applicant: Ravindranath Droopad ,  Matthias Passlack ,  Karthik Rajagopalan

Inventor： Ravindranath Droopad ,  Matthias Passlack ,  Karthik Rajagopalan

IPC: H01L21/336 ,  H01L31/00

CPC classification number: H01L29/155 ,  H01L29/66462

Abstract: A method of forming a semiconductor structure includes forming a channel layer; forming a superlattice barrier layer overlying the channel layer, and forming a gate dielectric overlying the superlattice barrier layer. The superlattice barrier layer includes alternating first and second layers of barrier material. In addition, the superlattice barrier layer is configured for increasing a transconductance of the semiconductor device by at least a factor of three over a semiconductor device absent such superlattice barrier layer.

Abstract translation: 形成半导体结构的方法包括形成沟道层; 形成覆盖所述沟道层的超晶格势垒层，以及形成覆盖所述超晶格势垒层的栅极电介质。 超晶格势垒层包括交替的第一和第二层屏障材料。 此外，超晶格势垒层被配置为在没有这种超晶格势垒层的半导体器件上将半导体器件的跨导增加至少三分之一。

公开(公告)号：US20090032802A1

公开(公告)日：2009-02-05

申请号：US11831394

申请日：2007-07-31

Applicant: Ravindranath Droopad ,  Matthias Passlack ,  Karthik Rajagopalan

Inventor： Ravindranath Droopad ,  Matthias Passlack ,  Karthik Rajagopalan

IPC: H01L29/15 ,  H01L21/336

CPC classification number: H01L29/155 ,  H01L29/66462

Abstract: A method of forming a semiconductor structure comprises forming a channel layer; forming a superlattice barrier layer overlying the channel layer, and forming a gate dielectric overlying the superlattice barrier layer. The superlattice barrier layer includes a plurality of alternating first and second layers of barrier material. In addition, the superlattice barrier layer is configured for increasing a transconductance of the semiconductor device by at least a factor of three over a semiconductor device absent such superlattice barrier layer.

Abstract translation: 形成半导体结构的方法包括形成沟道层; 形成覆盖所述沟道层的超晶格势垒层，以及形成覆盖所述超晶格势垒层的栅极电介质。 超晶格阻挡层包括多个交替的第一和第二层屏障材料。 此外，超晶格势垒层被配置为在没有这种超晶格势垒层的半导体器件上将半导体器件的跨导增加至少三分之一。

公开(公告)号：US07432565B2

公开(公告)日：2008-10-07

申请号：US11236185

申请日：2005-09-27

Applicant: Matthias Passlack

Inventor： Matthias Passlack

IPC: H01L29/20

CPC classification number: H01L29/66522 ,  H01L21/7605 ,  H01L29/41775 ,  H01L29/7725

Abstract: A III-V based, implant free MOS heterostructure field-effect transistor device comprises a gate insulator layer overlying a compound semiconductor substrate; ohmic contacts coupled to the compound semiconductor substrate proximate opposite sides of an active device region defined within the compound semiconductor substrate; and a gate metal contact electrode formed on the gate insulator layer in a region between the ohmic contacts. The ohmic contacts have portions thereof that overlap with portions of the gate insulator layer within the active device region. The overlapping portions ensure avoidance of an undesirable gap formation between an edge of the ohmic contact and a corresponding edge of the gate insulator layer.

Abstract translation: 一种基于III-V的无植入物的MOS异质结场场效应晶体管器件包括覆盖在化合物半导体衬底上的栅极绝缘体层; 耦合到化合物半导体衬底的欧姆接触靠近在化合物半导体衬底内限定的有源器件区域的相对侧; 以及栅极金属接触电极，形成在欧姆接触之间的区域中的栅极绝缘体层上。 欧姆接触件具有与有源器件区域内的栅极绝缘体层的部分重叠的部分。 重叠部分确保避免在欧姆接触的边缘和栅极绝缘体层的相应边缘之间形成不期望的间隙。

公开(公告)号：US20070090405A1

公开(公告)日：2007-04-26

申请号：US11236187

申请日：2005-09-27

Applicant: Matthias Passlack ,  Ravindranath Droopad ,  Karthik Rajagopalan

Inventor： Matthias Passlack ,  Ravindranath Droopad ,  Karthik Rajagopalan

IPC: H01L23/58

CPC classification number: H01L29/66462 ,  H01L21/02178 ,  H01L21/02222 ,  H01L21/02362 ,  H01L21/28264 ,  H01L21/318 ,  H01L29/517 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming a semiconductor structure comprises providing an insulator layer overlying a III-V compound substrate, the insulator layer having a surface charge layer, the surface charge layer having a deleterious performance effect on the underlying layer or layers of the III-V compound substrate. The method further comprises transforming the surface charge layer into a passivated surface layer, wherein the passivated surface layer reduces the deleterious performance effect on the underlying layer or layers.

Abstract translation: 形成半导体结构的方法包括提供覆盖III-V复合衬底的绝缘体层，所述绝缘体层具有表面电荷层，所述表面电荷层对III-V族化合物的下层或多层具有有害的性能作用 基质。 该方法还包括将表面电荷层转化为钝化表面层，其中钝化表面层减少对下层或下层的有害性能影响。