公开(公告)号：US20070187139A1

公开(公告)日：2007-08-16

申请号：US11668331

申请日：2007-01-29

Applicant: Kuo-Ching Huang ,  Yu-Cheng Chang

Inventor： Kuo-Ching Huang ,  Yu-Cheng Chang

IPC: H05K1/00

CPC classification number: H05K1/147 ,  H04N1/00519 ,  H04N1/1017 ,  H04N1/193 ,  H04N2201/0081 ,  H05K1/144 ,  H05K2201/09109

Abstract: A bus structure includes multiple soft buses and a soft separation layer. These multiple soft buses are stacked side by side each other. The soft separation layer is sandwitched between two adjacent soft buses.

Abstract translation: 总线结构包括多个软总线和软分离层。 这些多条软总线并排堆叠。 软分离层在两个相邻的软总线之间被切换。

公开(公告)号：US20060048969A1

公开(公告)日：2006-03-09

申请号：US11136558

申请日：2005-05-25

Applicant: Kuo-Ching Huang ,  Yu-Cheng Chang

Inventor： Kuo-Ching Huang ,  Yu-Cheng Chang

IPC: H05K1/03

CPC classification number: H05K1/147 ,  H04N1/00519 ,  H04N1/1017 ,  H04N1/193 ,  H04N2201/0081 ,  H05K1/144 ,  H05K2201/09109

Abstract: A bus structure includes multiple soft buses and a soft separation layer. These multiple soft buses are stacked side by side each other. The soft separation layer is sandwitched between two adjacent soft buses.

Abstract translation: 总线结构包括多个软总线和软分离层。 这些多条软总线并排堆叠。 软分离层在两个相邻的软总线之间被切换。

公开(公告)号：US06373369B2

公开(公告)日：2002-04-16

申请号：US09839927

申请日：2001-04-23

Applicant: Kuo-Ching Huang ,  Jin-Yuan Lee ,  Tse-Liang Ying

Inventor： Kuo-Ching Huang ,  Jin-Yuan Lee ,  Tse-Liang Ying

IPC: H01F500

CPC classification number: H01F5/003

Abstract: An improved thin film inductor design is described. A spiral geometry is used to which has been added a core of high permeability material located at the center of the spiral. If the high permeability material is a conductor, care must be taken to avoid any contact between the core and the spiral. If a dielectric ferromagnetic material is used, this constraint is removed from the design. Several other embodiments are shown in which, in addition to the high permeability core, provide low reluctance paths for the structure. In one case this takes the form of a frame of ferromagnetic material surrounding the spiral while in a second case it has the form of a hollow square located directly above the spiral.

Abstract translation: 描述了改进的薄膜电感器设计。 使用螺旋几何形状，其中已经添加了位于螺旋中心的高磁导率材料的核心。 如果高导磁率材料是导体，则必须注意避免芯和螺旋之间的任何接触。 如果使用介电铁磁材料，则从设计中去除该约束。 示出了其中除了高磁导率芯之外还提供用于结构的低磁阻路径的其它实施例。 在一种情况下，这采取围绕螺旋的铁磁材料框架的形式，而在第二种情况下，其具有直接位于螺旋上方的中空正方形的形式。

公开(公告)号：US06287939B1

公开(公告)日：2001-09-11

申请号：US09216789

申请日：1998-12-21

Applicant: Kuo Ching Huang ,  Tse-Liang Ying ,  Wen-Chuan Chiang

Inventor： Kuo Ching Huang ,  Tse-Liang Ying ,  Wen-Chuan Chiang

IPC: H01L2176

CPC classification number: H01L21/76224 ,  H01L21/76895

Abstract: The invention provides a method for fabricating a shallow trench isolation which is not susceptable to buried contact trench formation. The invention also provides immunity from the STI “kink effect,” as well as benefits associated with nitridation. The process begins by forming a pad oxide layer on a semiconductor substrate. A nitride layer is formed on the pad oxide layer. The nitride layer, the pad oxide layer, and the semiconductor substrate are patterned to form trenches. Next, a fill oxide layer is formed over the nitride layer, the pad oxide layer, and the semiconductor substrate. The fill oxide layer is chemical-mechanical polished, stopping on the nitride layer to form fill oxide regions. N2 ions are implanted into the fill oxide regions. An anneal is performed to form a buried oxynitride layer. The buried oxynitride layer is partially above the level of the top surface of the semiconductor substrate and partially below the level of the top surface of the semiconductor substrate. The nitride layer is removed. Then, the pad oxide layer and portions of the fill oxide regions are removed using the buried oxynitride layer as an etch stop, forming shallow trench isolations.

Abstract translation: 本发明提供一种用于制造不易于埋入接触沟槽形成的浅沟槽隔离的方法。 本发明还提供了对STI“扭结效应”的免疫力以及与氮化相关的益处。 该过程开始于在半导体衬底上形成衬垫氧化物层。 在衬垫氧化物层上形成氮化物层。 图案化氮化物层，衬垫氧化物层和半导体衬底以形成沟槽。 接下来，在氮化物层，衬垫氧化物层和半导体衬底之上形成填充氧化物层。 填充氧化物层进行化学机械抛光，在氮化物层上停止形成填充氧化物区域。 将N 2离子注入填充氧化物区域。 进行退火以形成掩埋的氮氧化物层。 掩埋的氧氮化物层部分地高于半导体衬底的顶表面的高度，并且部分地低于半导体衬底的顶表面的水平。 去除氮化物层。 然后，使用掩埋氧氮化物层作为蚀刻停止层，去除衬垫氧化物层和填充氧化物区域的部分，形成浅沟槽隔离。

公开(公告)号：US06214715B1

公开(公告)日：2001-04-10

申请号：US09349841

申请日：1999-07-08

Applicant: Kuo-Ching Huang ,  Tse-Liang Ying ,  Wen-Chuan Chiang

Inventor： Kuo-Ching Huang ,  Tse-Liang Ying ,  Wen-Chuan Chiang

IPC: H01L2144

CPC classification number: H01L27/10855 ,  H01L21/76897 ,  H01L27/10885 ,  H01L28/91 ,  H01L28/92

Abstract: This invention provides a method for forming a self aligned contact without key holes using a two step sidewall spacer deposition. The process begins by providing a semiconductor structure having a device layer, a first inter poly oxide layer (IPO-1), and a conductive structure (such as a bit line) thereover, and having a contact area on the device layer adjacent to the conductive structure. The semiconductor structure can further include an optional etch stop layer overlying the first inter poly oxide layer. The conductive structure comprises at least one conductive layer with a hard mask thereover. A first spacer layer is formed over the hard mask and the IPO-1 layer and anisotropically etched to form first sidewall spacers on the sidewalls of the conductive structure up to a level above the bottom of the hard mask and below the level of the top of the hard mask such that the profile of the first sidewall spacers are not concave at any point. A second spacer layer is formed over the first sidewall spacers and anisotropically etched to form second sidewall spacers, having a profile that is not concave at any point. A second inter poly oxide layer is formed over the second sidewall spacers, the hard mask, and the IPO-1 layer, whereby the second inter poly oxide layer is free from key holes. A contact opening is formed in the second inter poly oxide layer and the first inter poly oxide layer over the contact area. A contact plug is formed in the contact openings.

Abstract translation: 本发明提供一种用于使用两步侧壁间隔物沉积形成无键孔的自对准接触的方法。 该过程开始于提供具有器件层，第一多晶硅氧化物层（IPO-1）和导电结构（例如位线）的半导体结构，并且在与其相邻的器件层上具有接触区域 导电结构。 半导体结构还可以包括覆盖在第一多晶硅氧化物层上的任选的蚀刻停止层。 导电结构包括至少一个具有硬掩模的导电层。 在硬掩模和IPO-1层上形成第一间隔层，并且各向异性蚀刻以在导电结构的侧壁上形成直到硬掩模的底部以上的水平并且低于 硬掩模，使得第一侧壁隔片的轮廓在任何点都不是凹的。 第二间隔层形成在第一侧壁间隔物上并且各向异性蚀刻以形成第二侧壁间隔物，其具有在任何点处不凹的轮廓。 在第二侧壁间隔物，硬掩模和IPO-1层上形成第二多晶硅氧化物层，由此第二多晶氧化物层没有键孔。 在接触区域上的第二多晶氧化物层和第一多晶氧化物层中形成接触开口。 在接触开口中形成接触塞。

公开(公告)号：US6080637A

公开(公告)日：2000-06-27

申请号：US206736

申请日：1998-12-07

Applicant: Kuo Ching Huang ,  Tse-Liang Ying ,  Wen-Chuan Chiang ,  Cheng-Yeh Shih

Inventor： Kuo Ching Huang ,  Tse-Liang Ying ,  Wen-Chuan Chiang ,  Cheng-Yeh Shih

IPC: H01L21/762 ,  H01L21/76

CPC classification number: H01L21/76224 ,  Y10S148/05

Abstract: A process for creating an insulator filled, shallow trench, in a semiconductor substrate, in which the insulator layer in the shallow trench, is not exposed to procedures used to remove defining composite insulator layers, has been developed. The process features creating a lateral recess, in a thick silicon nitride layer, used as a component of a composite insulator layer, where the composite insulator layer is used for subsequent definition of the shallow trench, in the semiconductor substrate. An insulator deposition, filling openings, and recesses, in the composite insulator layer, and filling the shallow trench, followed by removal of excess insulator fill, on the top surface of the composite insulator layer, results in the formation of a "T" shape insulator, comprised of an insulator shape, in the shallow trench, and comprised of a wider insulator shape, located in the composite insulator shape, with the lateral recess in the thick silicon nitride layer, and with the wider insulator shape, overlying the narrow, insulator shape, in the shallow trench. The insulator, in the shallow trench, is protected from the procedure used to remove components of the composite insulator layer, by the wider insulator shape.

Abstract translation: 已经开发了在半导体衬底中形成绝缘体填充的浅沟槽的方法，其中浅沟槽中的绝缘体层不暴露于用于移除限定复合绝缘体层的程序。 该工艺的特征是在半导体衬底中产生在厚氮化硅层中用作复合绝缘体层的组分的横向凹槽，其中复合绝缘体层用于随后定义浅沟槽。 在复合绝缘体层中的绝缘体沉积，填充开口和凹陷，以及填充浅沟槽，然后在复合绝缘体层的顶表面上除去多余的绝缘体填充物，导致形成“T”形 绝缘体，由绝缘体形状构成，位于浅沟槽中，并且由更宽的绝缘体形状组成，位于复合绝缘体形状中，侧壁凹陷在厚氮化硅层中，并且具有更宽的绝缘体形状， 绝缘体形状，在浅沟槽。 通过更宽的绝缘体形状，在浅沟槽中的绝缘体被保护以避免用于去除复合绝缘体层的部件的程序。

公开(公告)号：US5998269A

公开(公告)日：1999-12-07

申请号：US35139

申请日：1998-03-05

Applicant: Kuo-Ching Huang ,  Shou-Gwo Wuu ,  Jenn-Ming Huang ,  Dun-Nian Yaung

Inventor： Kuo-Ching Huang ,  Shou-Gwo Wuu ,  Jenn-Ming Huang ,  Dun-Nian Yaung

IPC: H01L21/285 ,  H01L21/336 ,  H01L21/768 ,  H01L21/8244 ,  H01L21/3215 ,  H01L21/335 ,  H01L21/74

CPC classification number: H01L27/11 ,  H01L21/28512 ,  H01L21/76895 ,  H01L29/66545

Abstract: A new method of forming an improved buried contact junction is described. A gate silicon oxide layer is provided over the surface of a semiconductor substrate. A polysilicon layer is deposited overlying the gate oxide layer. A hard mask layer is deposited overlying the polysilicon layer. The hard mask and polysilicon layers are etched away where they are not covered by a mask to form a polysilicon gate electrode and interconnection lines wherein gaps are left between the gate electrode and interconnection lines. A layer of dielectric material is deposited over the semiconductor substrate to fill the gaps. The hard mask layer is removed. The polysilicon layer is etched away where it is not covered by a buried contact mask to form an opening to the semiconductor substrate. Ions are implanted to form the buried contact. A refractory metal layer is deposited overlying the buried contact and the polysilicon gate electrode and interconnection lines and planarized to form polycide gate electrodes and interconnection lines. The dielectric material layer is removed. An oxide layer is deposited and anisotropically etched to leave spacers on the sidewalls of the polycide gate electrodes and interconnection lines to complete the formation of a buried contact junction in the fabrication of an integrated circuit.

Abstract translation: 描述了形成改进的埋地接触结的新方法。 在半导体衬底的表面上设置栅极氧化硅层。 沉积在栅极氧化物层上的多晶硅层。 覆盖多晶硅层的硬掩模层被沉积。 硬掩模和多晶硅层被蚀刻掉，其中它们不被掩模覆盖以形成多晶硅栅电极和互连线，其中间隙留在栅电极和互连线之间。 介电材料层沉积在半导体衬底上以填补间隙。 去除硬掩模层。 多晶硅层被蚀刻掉，其未被掩埋的接触掩模覆盖，以形成到半导体衬底的开口。 植入离子以形成埋入的接触。 沉积覆盖在掩埋触点和多晶硅栅电极和互连线上的难熔金属层并且被平坦化以形成多晶硅栅极电极和互连线。 去除介电材料层。 沉积氧化物层并各向异性蚀刻以在多晶硅栅极电极和互连线的侧壁上留下间隔物，以在集成电路的制造中完成掩埋接触结的形成。

公开(公告)号：US20080318454A1

公开(公告)日：2008-12-25

申请号：US11766204

申请日：2007-06-21

Applicant: Chen-Fa Wu ,  Chih-Nan Lin ,  Kuo-Ching Huang ,  Chin-An Huang

Inventor： Chen-Fa Wu ,  Chih-Nan Lin ,  Kuo-Ching Huang ,  Chin-An Huang

IPC: H01R12/16

CPC classification number: H05K1/0271 ,  H05K2201/044 ,  H05K2201/09063 ,  H05K2201/10409 ,  H05K2201/10734

Abstract: An information handling system circuit board has an opening formed through it proximate a coupling point of an integrated circuit to the circuit board. The opening manages stress at the coupling point of the integrated circuit to the circuit board to reduce the risk of damage to the coupling point during deformation of the circuit board, such as when the circuit board is coupled to a chassis or when a component is pressed into the circuit board. In one embodiment, rectangular openings are formed at diagonally opposed corners of a BSA integrated circuit. In alternative embodiments, openings of varying shape, such as slots or curved slots, are formed at selected corners of the integrated circuit.

Abstract translation: 信息处理系统电路板具有通过其形成的开口，其靠近集成电路到电路板的耦合点。 开口处理集成电路到电路板的耦合点处的应力，以减少在电路板变形期间对耦合点的损坏的风险，例如当电路板耦合到底盘或当部件被按压时 进入电路板。 在一个实施例中，在BSA集成电路的对角相对的角上形成矩形开口。 在替代实施例中，在集成电路的选定角处形成变化形状的开口，例如槽或弯曲槽。

公开(公告)号：US20060061837A1

公开(公告)日：2006-03-23

申请号：US10904740

申请日：2004-11-24

Applicant: Kuo-Ching Huang ,  Yu-Cheng Chang

Inventor： Kuo-Ching Huang ,  Yu-Cheng Chang

IPC: H04N1/23

CPC classification number: H04N1/1013 ,  H04N2201/0406 ,  H04N2201/0408 ,  H04N2201/0422

Abstract: A clamp for fixing a photographic slide and/or a photographic negative includes a carrier and a cover for fixing the slide or negative onto the carrier. The carrier includes a first guide for holding the negative, and a second guide extended from the first guide for holding the photographic slide.

Abstract translation: 用于固定照相底片和/或照相底片的夹具包括用于将滑块或阴极固定到载体上的载体和盖。 载体包括用于保持负片的第一引导件和从第一引导件延伸以保持照相载玻片的第二引导件。

公开(公告)号：US6037222A

公开(公告)日：2000-03-14

申请号：US83271

申请日：1998-05-22

Applicant: Kuo Ching Huang ,  Tse-Liang Ying ,  Chen-Jong Wang ,  Jenn Ming Huang

Inventor： Kuo Ching Huang ,  Tse-Liang Ying ,  Chen-Jong Wang ,  Jenn Ming Huang

IPC: H01L21/8239 ,  H01L21/8242 ,  H01L21/336 ,  H01L21/8234

CPC classification number: H01L27/10894 ,  H01L27/1052 ,  H01L27/10873

Abstract: A method of manufacturing a memory device having embedded logic. The memory and logic FETS have two different two gate oxide 20 34 thicknesses. The method integrates (1) a salicide contact process 72 74 (logic devices) and dual gate (N+/P+) logic gate 24A 24B technology with (2) memory device Polycide with Self aligned Contact 80 Technology. The method comprises:(a) forming a first gate oxide layer 20, a first polysilicon layer 24, and a first gate cap layer 28 over said logic area 12;(b) forming memory gate structures 34 36 38 40 42A in memory area 14,(c) forming memory LDD regions 50 adjacent to said memory gate structures 24 26 28 40 in said memory area 14;(d) patterning said first gate oxide layer 20, said first polysilicon layer 24 and said first gate cap layer 28 over said logic area forming logic gate structures 20 24A & 20 24B;(e) forming spacers 66;(f) forming logic Source/drain regions 62;(g) using a salicide process to form self-aligned silicide logic S/D contacts 72 to said Source/drain regions 62, and to form self-aligned silicide logic gate contacts 74 to said logic gate structures 20 24B & 20 24A; and(h) forming self aligned polycide contacts 80 to said memory source/drain regions 50.

Abstract translation: 一种制造具有嵌入式逻辑的存储器件的方法。 存储器和逻辑FETs具有两个不同的两个栅极氧化层20 34的厚度。 该方法集成了（1）自杀式接触过程72 74（逻辑器件）和双栅极（N + / P +）逻辑门24A 24B技术与（2）存储器件Polycide与自对准接触80技术。 该方法包括：（a）在所述逻辑区域12上形成第一栅极氧化物层20，第一多晶硅层24和第一栅极覆盖层28; （b）在存储器区域14中形成存储器栅极结构34 36 38 40 42A，（c）在所述存储区域14中形成与所述存储器栅极结构24 26 28 40相邻的存储器LDD区域50; （d）在所述逻辑区域上形成所述第一栅极氧化物层20，所述第一多晶硅层24和所述第一栅极覆盖层28，形成逻辑门结构20A，24A和20BB; （e）形成间隔件66; （f）形成逻辑源极/漏极区域62; （g）使用自对准硅化物工艺将自对准硅化物逻辑S / D触点72形成到所述源极/漏极区62，并且形成到所述逻辑门结构20 24B和20 24A的自对准硅化物逻辑门触点74; 和（h）将自对准的多晶硅触点80形成到所述存储器源极/漏极区50。