知搜-全球专利检索

  1. Login
  2. Sign Up

Search Results

899 records (took 0.037 seconds)

    METHOD OF MULTIPLE PATTERNING TO FORM SEMICONDUCTOR DEVICES
    21.
    发明申请
    METHOD OF MULTIPLE PATTERNING TO FORM SEMICONDUCTOR DEVICES 有权
    多种图案形成半导体器件的方法

    公开(公告)号：US20140024191A1

    公开(公告)日：2014-01-23

    申请号：US13555240

    申请日：2012-07-23

    Applicant: Kuang-Jung Chen ,  Kangguo Cheng ,  Bruce B. Doris ,  Steven J. Holmes ,  Sen Liu

    Inventor： Kuang-Jung Chen ,  Kangguo Cheng ,  Bruce B. Doris ,  Steven J. Holmes ,  Sen Liu

    IPC: H01L21/31 ,  H01L21/336

    CPC classification number: H01L21/0274 ,  H01L21/26586 ,  H01L21/3081 ,  H01L21/76229 ,  H01L21/76283 ,  H01L29/517 ,  H01L29/66575 ,  H01L29/78

    Abstract: A method of forming different structures of a semiconductor device using a single mask and a hybrid photoresist. The method includes: applying a first photoresist layer on a semiconductor substrate; patterning the first photoresist layer using a photomask to form a first patterned photoresist layer; using the first patterned photoresist layer to form a first structure of a semiconductor device; removing the first patterned photoresist layer; applying a second photoresist layer on the semiconductor substrate; patterning the second photoresist layer using the photomask to form a second patterned photoresist layer; using the second patterned photoresist layer to form a second structure of a semiconductor device; removing the second patterned photoresist layer; and wherein either the first or the second photoresist layer is a hybrid photoresist layer comprising a hybrid photoresist.

    Abstract translation: 使用单个掩模和混合光致抗蚀剂形成半导体器件的不同结构的方法。 该方法包括：在半导体衬底上施加第一光致抗蚀剂层; 使用光掩模图案化第一光致抗蚀剂层以形成第一图案化光致抗蚀剂层; 使用所述第一图案化的光致抗蚀剂层形成半导体器件的第一结构; 去除第一图案化光致抗蚀剂层; 在所述半导体衬底上施加第二光致抗蚀剂层; 使用光掩模图案化第二光致抗蚀剂层以形成第二图案化光致抗蚀剂层; 使用所述第二图案化的光致抗蚀剂层形成半导体器件的第二结构; 去除第二图案化光致抗蚀剂层; 并且其中所述第一或第二光致抗蚀剂层是包含混合光致抗蚀剂的混合光致抗蚀剂层。

    Extremely thin semiconductor-on-insulator (ETSOI) integrated circuit with on-chip resistors and method of forming the same
    22.
    发明授权
    Extremely thin semiconductor-on-insulator (ETSOI) integrated circuit with on-chip resistors and method of forming the same 有权
    具有片上电阻的非常薄的绝缘体上半导体（ETSOI）集成电路及其形成方法

    公开(公告)号：US08629504B2

    公开(公告)日：2014-01-14

    申请号：US13433401

    申请日：2012-03-29

    Applicant: Bruce B. Doris ,  Kangguo Cheng ,  Ali Khakifirooz ,  Ghavam G. Shahidi

    Inventor： Bruce B. Doris ,  Kangguo Cheng ,  Ali Khakifirooz ,  Ghavam G. Shahidi

    IPC: H01L21/00

    CPC classification number: H01L27/1214 ,  H01L21/84 ,  H01L27/1203 ,  H01L27/13

    Abstract: An electrical device is provided that in one embodiment includes a semiconductor-on-insulator (SOI) substrate having a semiconductor layer with a thickness of less than 10 nm. A semiconductor device having a raised source region and a raised drain region of a single crystal semiconductor material of a first conductivity is present on a first surface of the semiconductor layer. A resistor composed of the single crystal semiconductor material of the first conductivity is present on a second surface of the semiconductor layer. A method of forming the aforementioned electrical device is also provided.

    Abstract translation: 提供了一种电气装置，其在一个实施例中包括具有厚度小于10nm的半导体层的绝缘体上半导体（SOI）基板。 在半导体层的第一表面上存在具有第一导电性的单晶半导体材料的升高的源极区域和升高的漏极区域的半导体器件。 由第一导电性的单晶半导体材料构成的电阻器存在于半导体层的第二表面上。 还提供了形成上述电气装置的方法。

    UNDERCUT INSULATING REGIONS FOR SILICON-ON-INSULATOR DEVICE
    23.
    发明申请
    UNDERCUT INSULATING REGIONS FOR SILICON-ON-INSULATOR DEVICE 有权
    用于绝缘体绝缘体器件的绝缘绝缘区域

    公开(公告)号：US20140001555A1

    公开(公告)日：2014-01-02

    申请号：US13537141

    申请日：2012-06-29

    Applicant: Kangguo Cheng ,  Bruce B. Doris ,  Balasubramanian S. Haran ,  Shom Ponoth ,  Theodorus E. Standaert ,  Tenko Yamashita

    Inventor： Kangguo Cheng ,  Bruce B. Doris ,  Balasubramanian S. Haran ,  Shom Ponoth ,  Theodorus E. Standaert ,  Tenko Yamashita

    IPC: H01L29/78 ,  H01L21/336

    CPC classification number: H01L29/0649 ,  H01L21/76229 ,  H01L21/76232 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0653 ,  H01L29/41766 ,  H01L29/78 ,  H01L29/7838

    Abstract: A method of making a silicon-on-insulator (SOI) semiconductor device includes etching an undercut isolation trench into an SOI substrate, the SOI substrate comprising a bottom substrate, a buried oxide (BOX) layer formed on the bottom substrate, and a top SOI layer formed on the BOX layer, wherein the undercut isolation trench extends through the top SOI layer and the BOX layer and into the bottom substrate such that a portion of the undercut isolation trench is located in the bottom substrate underneath the BOX layer. The undercut isolation trench is filled with an undercut fill comprising an insulating material to form an undercut isolation region. A field effect transistor (FET) device is formed on the top SOI layer adjacent to the undercut isolation region, wherein the undercut isolation region extends underneath a source/drain region of the FET.

    Abstract translation: 制造绝缘体上硅（SOI）半导体器件的方法包括将底切隔离沟槽蚀刻成SOI衬底，所述SOI衬底包括底部衬底，形成在底部衬底上的掩埋氧化物（BOX）层，以及顶部 SOI层，其形成在BOX层上，其中底切隔离沟槽延伸穿过顶部SOI层和BOX层并进入底部衬底，使得底切绝缘沟槽的一部分位于BOX层下方的底部衬底中。 底切隔离槽填充有包括绝缘材料的底切填充物以形成底切隔离区域。 在与底切隔离区相邻的顶部SOI层上形成场效应晶体管（FET）器件，其中底切隔离区延伸在FET的源极/漏极区的下方。

    FinFET diode with increased junction area
    26.
    发明授权
    FinFET diode with increased junction area 失效
    FinFET二极管具有增加的接合面积

    公开(公告)号：US08592263B2

    公开(公告)日：2013-11-26

    申请号：US13456921

    申请日：2012-04-26

    Applicant: Theodorus Eduardus Standaert ,  Kangguo Cheng ,  Balasubramanian S. Haran ,  Shom Ponoth ,  Tenko Yamashita

    Inventor： Theodorus Eduardus Standaert ,  Kangguo Cheng ,  Balasubramanian S. Haran ,  Shom Ponoth ,  Tenko Yamashita

    IPC: H01L21/84

    CPC classification number: H01L29/861 ,  H01L21/845 ,  H01L27/0266 ,  H01L29/24 ,  H01L29/267 ,  H01L29/6609 ,  H01L29/785

    Abstract: A FinFET diode and method of fabrication are disclosed. In one embodiment, the diode comprises, a semiconductor substrate, an insulator layer disposed on the semiconductor substrate, a first silicon layer disposed on the insulator layer, a plurality of fins formed in a diode portion of the first silicon layer. A region of the first silicon layer is disposed adjacent to each of the plurality of fins. A second silicon layer is disposed on the plurality of fins formed in the diode portion of the first silicon layer. A gate ring is disposed on the first silicon layer. The gate ring is arranged in a closed shape, and encloses a portion of the plurality of fins formed in the diode portion of the first silicon layer.

    Abstract translation: 公开了一种FinFET二极管及其制造方法。 在一个实施例中，二极管包括半导体衬底，设置在半导体衬底上的绝缘体层，设置在绝缘体层上的第一硅层，形成在第一硅层的二极管部分中的多个鳍片。 第一硅层的区域设置成与多个翅片中的每一个相邻。 第二硅层设置在形成在第一硅层的二极管部分中的多个翅片上。 栅极环设置在第一硅层上。 门环布置成闭合形状，并且包围形成在第一硅层的二极管部分中的多个翅片的一部分。

    Self-aligned dual depth isolation and method of fabrication
    28.
    发明授权
    Self-aligned dual depth isolation and method of fabrication 失效
    自对准双深度隔离和制造方法

    公开(公告)号：US08587086B2

    公开(公告)日：2013-11-19

    申请号：US13598992

    申请日：2012-08-30

    Applicant: Kangguo Cheng ,  Robert Heath Dennard ,  Bruce B. Doris ,  Ali Khakifirooz ,  Ghavam G. Shahidi

    Inventor： Kangguo Cheng ,  Robert Heath Dennard ,  Bruce B. Doris ,  Ali Khakifirooz ,  Ghavam G. Shahidi

    IPC: H01L21/70

    CPC classification number: H01L21/84 ,  H01L21/3086 ,  H01L21/76283 ,  H01L27/1104

    Abstract: FDSOI devices and methods for the fabrication thereof are provided. In one aspect, a method for fabricating a device includes the following steps. A wafer is provided having a substrate, a BOX and a SOI layer. A hardmask layer is deposited over the SOI layer. A photoresist layer is deposited over the hardmask layer and patterned into groups of segments. A tilted implant is performed to damage all but those portions of the hardmask layer covered or shadowed by the segments. Portions of the hardmask layer damaged by the implant are removed. A first etch is performed through the hardmask layer to form a deep trench in the SOI layer, the BOX and at least a portion of the substrate. The hardmask layer is patterned using the patterned photoresist layer. A second etch is performed through the hardmask layer to form shallow trenches in the SOI layer.

    Abstract translation: 提供了FDSOI器件及其制造方法。 一方面，一种制造装置的方法包括以下步骤。 提供具有基板，BOX和SOI层的晶片。 硬掩模层沉积在SOI层上。 光致抗蚀剂层沉积在硬掩模层上并且被图案化成一组片段。 执行倾斜的植入物以损坏被片段覆盖或遮蔽的硬掩模层的所有部分。 移除由植入物损坏的硬掩模层的部分。 通过硬掩模层执行第一蚀刻，以在SOI层，BOX和衬底的至少一部分中形成深沟槽。 使用图案化的光致抗蚀剂层对硬掩模层进行图案化。 通过硬掩模层进行第二蚀刻，以在SOI层中形成浅沟槽。

    Method of fabricating field effect transistors with low k sidewall spacers
    29.
    发明授权
    Method of fabricating field effect transistors with low k sidewall spacers 失效
    制造具有低k侧壁间隔物的场效应晶体管的方法

    公开(公告)号：US08580646B2

    公开(公告)日：2013-11-12

    申请号：US12948805

    申请日：2010-11-18

    Applicant: Kangguo Cheng ,  Louis Lu-Chen Hsu ,  Jack A. Mandelman ,  William R. Tonti

    Inventor： Kangguo Cheng ,  Louis Lu-Chen Hsu ,  Jack A. Mandelman ,  William R. Tonti

    IPC: H01L21/336 ,  H01L21/331 ,  H01L21/425 ,  H01L21/26 ,  H01L21/42

    CPC classification number: H01L29/4983 ,  H01L21/26586 ,  H01L21/268 ,  H01L29/665

    Abstract: Field effect transistors and method for forming filed effect transistors. The field effect transistors including: a gate dielectric on a channel region in a semiconductor substrate; a gate electrode on the gate dielectric; respective source/drains in the substrate on opposite sides of the channel region; sidewall spacers on opposite sides of the gate electrode proximate to the source/drains; and wherein the sidewall spacers comprise a material having a dielectric constant lower than that of silicon dioxide and capable of absorbing laser radiation.

    Abstract translation: 场效应晶体管和形成场效应晶体管的方法。 场效应晶体管包括：半导体衬底中的沟道区上的栅极电介质; 栅电极上的栅电极; 在沟道区域的相对侧上的衬底中的相应源极/漏极; 靠近源极/漏极的栅电极的相对侧上的侧壁间隔物; 并且其中所述侧壁间隔物包括介电常数低于二氧化硅的介电常数且能够吸收激光辐射的材料。

Patent Agency Ranking