公开(公告)号：US10939059B2

公开(公告)日：2021-03-02

申请号：US16465218

申请日：2017-11-22

申请人： SHANGHAI IC R&D CENTER CO., LTD. ,  CHENGDU IMAGE DESIGN TECHNOLOGY CO. LTD.

发明人： Jiebin Duan ,  Zheng Ren ,  Yu Jiang ,  Jianxin Wen ,  Changming Pi

IPC分类号： H04N5/355 ,  H04N5/378 ,  H04N5/374 ,  H04N5/369

摘要： The present disclosure provides a global shutter CMOS pixel circuit and its image capturing method. The global shutter CMOS pixel circuit comprising a power supply unit, a pixel signal generating unit, a signal sampling and holding unit and a signal outputting unit. An output of the pixel signal generating unit is connected to an input of the signal sampling and holding unit. An output of the signal sampling and holding unit is connected to an input of the signal outputting unit. The output signal of the pixel and the photo-generated current are set to a logarithmic relationship, which effectively increases the signal dynamic range. Therefore, image signal transmission with high speed and high dynamic range can be achieved simultaneously. Furthermore, the pixels in the present disclosure can eliminate the process variations, which increases the consistency of the pixels.

公开(公告)号：US10796913B2

公开(公告)日：2020-10-06

申请号：US16330087

申请日：2017-06-06

申请人： SHANGHAI IC R&D CENTER CO., LTD.

发明人： Hong Lin

IPC分类号： H01L21/00 ,  H01L21/18 ,  H01L21/768 ,  H01L21/324

摘要： A method for hybrid wafer-to-wafer bonding, comprising: providing two silicon wafers with Cu pattern structures, a conventional Cu BEOL process is adopted on the silicon wafers to obtain the planarized surface with copper and dielectric; removing part of the Cu on the planarized surface of the Cu pattern structures by adopting an etching process to form a certain amount of Cu recesses; depositing a layer of bonding metal on the surface of the Cu by adopting a selective deposition process; performing surface activation on the bonding metal and the dielectric by adopting a surface activation process; aligning and pressing the two silicon wafers together to obtain the dielectric bonding; and obtaining the metal bonding through the annealing process. The sufficient metal bonding can be obtained at low annealing temperature according to the present invent, thereby the risk of dielectric delaminating caused by thermal expansion mismatch is reduced, which is conducive to reduce the difficulty of process integration, save process time and improve product yield.

公开(公告)号：US09536987B2

公开(公告)日：2017-01-03

申请号：US14764175

申请日：2014-11-24

申请人： SHANGHAI IC R & D CENTER CO., LTD.

发明人： Chunyan Yi ,  Ming Li

IPC分类号： H01L29/66 ,  H01L21/027 ,  H01L21/308 ,  H01L21/311

CPC分类号： H01L29/66795 ,  H01L21/0276 ,  H01L21/3086 ,  H01L21/31116 ,  H01L21/31138

摘要： A line-end cutting method for fin structures of FinFETs formed by double patterning technology firstly utilizes the SiN hard mask lines to form fin structures and then performs lithography and etching processes to form line-end cuts. Since the depth of the line-end cuts is large, there is enough time and space to regulate the etching recipe so as to balance the etching rate of multiple layers including the spin-on-carbon layer, the SiN layer, the SiO2 layer and the silicon substrate, thereby forming the fin structures with line-end cuts having flatter bottom topography, preventing the formation of silicon protrusions or silicon cones during the etching process and improving the device electrical performance.

摘要翻译： 通过双重图案化技术形成的FinFET翅片结构的线端切割方法首先利用SiN硬掩模线形成鳍结构，然后进行光刻和蚀刻工艺以形成线端切割。 由于线端切割的深度大，所以存在足够的时间和空间来调节蚀刻配方，以平衡包括自旋 - 碳层，SiN层，SiO 2层和 硅衬底，从而形成具有平坦底部形貌的线端切口的翅片结构，防止在蚀刻工艺期间形成硅突起或硅锥，并提高器件电性能。

公开(公告)号：US09471739B2

公开(公告)日：2016-10-18

申请号：US14363357

申请日：2012-11-20

申请人： SHANGHAI IC R&D CENTER CO., LTD.

发明人： Zheng Ren ,  Shaojian Hu ,  Wei Zhou ,  Shoumian Chen ,  Yuhang Zhao

IPC分类号： G06F17/50

CPC分类号： G06F17/5077 ,  G06F17/5009 ,  G06F17/5068 ,  G06F17/5081

摘要： A method is provided for designing an IC chip. The method includes receiving data from a pre-layout design process for the IC chip, routing a plurality of interconnecting wires to connect various devices of the IC chip, and extracting various circuit parameters. The method also includes simulating the IC chip using the extracted various circuit parameters to detect logic or timing error in the IC chip. The extracting the various circuit parameters includes establishing a statistical interconnect technology profile (ITP) file containing at least interconnect parasitic parameters based on correlations of interconnect layer geometric parameter variations.

摘要翻译： 提供了一种用于设计IC芯片的方法。 该方法包括从用于IC芯片的预布局设计过程接收数据，布线多条互连线以连接IC芯片的各种器件，以及提取各种电路参数。 该方法还包括使用提取的各种电路参数来模拟IC芯片来检测IC芯片中的逻辑或定时误差。 提取各种电路参数包括基于互连层几何参数变化的相关性来建立包含至少互连寄生参数的统计互连技术简档（ITP）文件。

公开(公告)号：US09466699B2

公开(公告)日：2016-10-11

申请号：US15033097

申请日：2014-07-18

申请人： SHANGHAI IC&D CENTER CO., LTD.

发明人： Ao Guo ,  Zheng Ren ,  Shaojian Hu ,  Wei Zhou

IPC分类号： H01L21/336 ,  H01L29/66 ,  H01L29/786 ,  H01L29/78 ,  H01L29/423 ,  H01L27/12 ,  H01L21/265 ,  H01L21/02 ,  H01L21/3105

CPC分类号： H01L29/66666 ,  H01L21/02233 ,  H01L21/0228 ,  H01L21/265 ,  H01L21/31055 ,  H01L27/1203 ,  H01L29/0669 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/7827 ,  H01L29/78642

摘要： A manufacturing method is provided for fabricating a vertical channel gate-all-around MOSFET by epitaxy processes. The method includes growing a first epitaxial layer on a top semiconducting layer of a substrate; etching the first epitaxial layer and the top layer to form a first source/drain pattern in the top layer; etching the first epitaxial layer to form a vertical channel structure; then forming a gate dielectric layer on the vertical channel structure surface; forming a sandwich structure composed of a bottom spacer layer, a gate electrode layer and a top spacer layer; etching the top spacer layer and the gate electrode layer to form a gate pattern followed by forming a top spacer structure thereon; growing a second epitaxial layer and etching to form a second source/drain pattern.

摘要翻译： 提供了通过外延工艺制造垂直沟道栅极全面MOSFET的制造方法。 该方法包括在衬底的顶部半导体层上生长第一外延层; 蚀刻第一外延层和顶层以在顶层中形成第一源极/漏极图案; 蚀刻第一外延层以形成垂直沟道结构; 然后在垂直沟道结构表面上形成栅极电介质层; 形成由底部间隔层，栅极电极层和顶部间隔层组成的夹层结构; 蚀刻顶部间隔层和栅电极层以形成栅极图案，随后在其上形成顶部间隔结构; 生长第二外延层和蚀刻以形成第二源极/漏极图案。

公开(公告)号：US09305951B2

公开(公告)日：2016-04-05

申请号：US14439229

申请日：2012-12-28

申请人： Xiaoxu Kang ,  Yuhang Zhao

发明人： Xiaoxu Kang ,  Yuhang Zhao

IPC分类号： H01L27/146

CPC分类号： H01L27/14623 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/14629 ,  H01L27/14636 ,  H01L27/14645 ,  H01L27/14685 ,  H01L27/14689

摘要： A pixel structure of a CMOS image sensor pixel structure and a manufacturing method thereof. The structure comprises a photosensitive element (37) and a multi-layer structure of a standard CMOS device arranged on the silicon substrate (31). A deep groove (38) having a light-transmitting space therein is formed above the photosensitive element, a side wall of the deep groove is surrounded by a light reflection shielding layer (39) continuously arranged in a longitudinal direction to reflect the light incident on the light reflection shielding layer. The side wall of the deep groove is surrounded by metal interconnects, vias, contact holes and polysilicon in annular configurations, thus the incident light on the deep grove is substantially completely reflected, which avoids the optical crosstalk and effectively improves the optical resolution and sensitivity of the pixel and the performance and reliability of the chip.

摘要翻译： CMOS图像传感器像素结构的像素结构及其制造方法。 该结构包括光敏元件（37）和布置在硅衬底（31）上的标准CMOS器件的多层结构。 在感光元件的上方形成有具有透光空间的深槽（38），深槽的侧壁由沿纵向方向连续排列的光反射屏蔽层（39）包围，以反射入射到 光反射屏蔽层。 深槽的侧壁由金属互连，通孔，接触孔和环状构造的多晶硅围绕，因此深沟槽中的入射光基本上完全反射，从而避免了光学串扰，并有效提高了光学分辨率和灵敏度 像素和芯片的性能和可靠性。

公开(公告)号：US09269613B2

公开(公告)日：2016-02-23

申请号：US14125314

申请日：2011-12-20

申请人： Yuhang Zhao ,  Xiaoxu Kang

发明人： Yuhang Zhao ,  Xiaoxu Kang

IPC分类号： H01L21/768 ,  H01L23/532 ,  H01L23/528

CPC分类号： H01L21/7682 ,  H01L21/76804 ,  H01L21/76807 ,  H01L23/528 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method is disclosed for manufacturing a semiconductor device with a copper interconnect structure. The method includes providing a substrate, forming a first interconnect dielectric layer on the substrate, and forming a second interconnect dielectric layer on a surface of the first interconnect dielectric layer. The method also includes forming a plurality of conduits extending through the first interconnect dielectric layer and the second interconnect dielectric layer, and depositing copper in the plurality of conduits to form a copper interconnect layer of the copper interconnect structure. Further, the first interconnect dielectric layer, between neighboring conduits, contains cavities such that dielectric constant of the first interconnect dielectric layer is reduced. The second interconnect dielectric layer seals the top of the cavities, the substrate is the bottom of the cavities, and a width of the top of the cavities is less than a width of the bottom of the cavities.

摘要翻译： 公开了一种用于制造具有铜互连结构的半导体器件的方法。 该方法包括提供衬底，在衬底上形成第一互连电介质层，以及在第一互连电介质层的表面上形成第二互连电介质层。 该方法还包括形成延伸穿过第一互连电介质层和第二互连电介质层的多个导管，以及在多个导管中沉积铜以形成铜互连结构的铜互连层。 此外，相邻导管之间的第一互连电介质层包含空腔，使得第一互连电介质层的介电常数降低。 第二互连电介质层密封空腔的顶部，衬底是空腔的底部，并且空腔的顶部的宽度小于腔的底部的宽度。

公开(公告)号：US20140351779A1

公开(公告)日：2014-11-27

申请号：US14363357

申请日：2012-11-20

申请人： SHANGHAI IC R&D CENTER CO., LTD.

发明人： Zheng Ren ,  Shaojian Hu ,  Wei Zhou ,  Shoumian Chen ,  Yuhang Zhao

IPC分类号： G06F17/50

CPC分类号： G06F17/5077 ,  G06F17/5009 ,  G06F17/5068 ,  G06F17/5081

摘要： A method is provided for designing an IC chip. The method includes receiving data from a pre-layout design process for the IC chip, routing a plurality of interconnecting wires to connect various devices of the IC chip, and extracting various circuit parameters. The method also includes simulating the IC chip using the extracted various circuit parameters to detect logic or timing error in the IC chip. The extracting the various circuit parameters includes establishing a statistical interconnect technology profile (ITP) file containing at least interconnect parasitic parameters based on correlations of interconnect layer geometric parameter variations.

摘要翻译： 提供了一种用于设计IC芯片的方法。 该方法包括从用于IC芯片的预布局设计过程接收数据，布线多条互连线以连接IC芯片的各种器件，以及提取各种电路参数。 该方法还包括使用提取的各种电路参数来模拟IC芯片来检测IC芯片中的逻辑或定时误差。 提取各种电路参数包括基于互连层几何参数变化的相关性来建立包含至少互连寄生参数的统计互连技术简档（ITP）文件。

公开(公告)号：US20140217550A1

公开(公告)日：2014-08-07

申请号：US13884970

申请日：2012-02-07

申请人： Qingyun Zuo ,  Xiaoxu Kang ,  Shaohai Zeng

发明人： Qingyun Zuo ,  Xiaoxu Kang ,  Shaohai Zeng

IPC分类号： H01L49/02

CPC分类号： H01L28/20 ,  H01L23/5228 ,  H01L23/53238 ,  H01L28/24 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method is provided for manufacturing a semiconductor device with a metal film resistor structure. The method includes providing an insulation layer on the semiconductor device. A lower copper interconnect is formed in the insulation layer. The method also includes forming a cap layer on the insulation layer and the lower copper interconnect and etching the cap layer based on a single photolithography mask to form a window exposing portion of the lower copper interconnect and portion of the insulation layer. Further, the method includes forming a metal film layer on the cap layer and inside the window such that exposed portion of the lower copper interconnect is connected with part of the metal film layer within the window. The method also includes performing a chemical mechanical polishing (CMP) process to form a metal film resistor based on the metal film layer. The metal film resistor is connected with the portion of the lower copper interconnect.

摘要翻译： 提供一种用于制造具有金属膜电阻器结构的半导体器件的方法。 该方法包括在半导体器件上提供绝缘层。 在绝缘层中形成较低的铜互连。 该方法还包括在绝缘层和下铜互连上形成覆盖层，并且基于单个光刻掩模蚀刻覆盖层以形成下铜互连和绝缘层的一部分的窗口暴露部分。 此外，该方法包括在盖层和窗内部形成金属膜层，使得下铜互连的暴露部分与窗内的金属膜层的一部分连接。 该方法还包括进行化学机械抛光（CMP）工艺以形成基于金属膜层的金属膜电阻器。 金属膜电阻器与下部铜互连部分连接。

公开(公告)号：US20140151455A1

公开(公告)日：2014-06-05

申请号：US13884969

申请日：2011-03-14

申请人： Chen Li ,  Yong Wang ,  Shoumian Chen

发明人： Chen Li ,  Yong Wang ,  Shoumian Chen

IPC分类号： G06K19/077

CPC分类号： G06K19/07771 ,  G06K19/0775 ,  G06K19/07775

摘要： A radio frequency identification (RFID) device is disclosed. The RFID device includes a silicon substrate having a top side and a bottom side. The RFID device also includes a plurality of circuitry layers formed on the top side of the substrate, and the plurality of circuitry layers include at least a core circuitry and an on-chip antenna. Further, the RFID device includes a plurality of deep openings formed in the substrate on the bottom side under the plurality of circuitry layers. The plurality of deep openings are arranged in an array and through a substantial portion of the substrate, and a remaining portion of the substrate unreached by the plurality of deep openings separates the plurality of deep openings and the plurality of circuitry layers.

摘要翻译： 公开了射频识别（RFID）设备。 RFID装置包括具有顶侧和底侧的硅衬底。 RFID设备还包括形成在衬底的顶侧上的多个电路层，并且多个电路层至少包括核心电路和片上天线。 此外，RFID装置包括在多个电路层下方的底侧上的基板中形成的多个深开口。 多个深开口以阵列布置并且穿过基底的大部分，并且未被多个深开口未被接触的基底的剩余部分分离出多个深开口和多个电路层。