公开(公告)号：US09312223B2

公开(公告)日：2016-04-12

申请号：US14125313

申请日：2011-12-31

申请人： Yuhang Zhao ,  Xiaoxu Kang

发明人： Yuhang Zhao ,  Xiaoxu Kang

IPC分类号： H01L23/532 ,  H01L21/768 ,  H01L21/285 ,  H01L23/522

CPC分类号： H01L23/53276 ,  H01L21/28562 ,  H01L21/76801 ,  H01L21/7682 ,  H01L21/76838 ,  H01L21/7684 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76895 ,  H01L23/5222 ,  H01L23/53295 ,  H01L2221/1094 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention relates to an interconnection structure and a method for fabricating the same. According to the present invention, cavities are formed between the interconnection dielectric by using a sacrificial layer, carbon nanotubes are used as the interconnection material for local interconnection between via holes, graphene nanoribbons are used as the interconnection material for metal lines, and cavities are included in the interconnection dielectric. In addition, the conventional CMOS BEOL Cu interconnection technique is applied to the intermediate interconnection level and the global interconnection level. In this way, the high parasitic resistance and parasitic capacitance in the Cu interconnection technique, which may occur when the local interconnection is relatively small in size, can be effectively overcome.

摘要翻译： 互连结构及其制造方法技术领域本发明涉及互连结构及其制造方法。 根据本发明，通过使用牺牲层在互连电介质之间形成空腔，碳纳米管用作用于通孔之间的局部互连的互连材料，石墨烯纳米带用作金属线的互连材料，并且包括空腔 在互连电介质中。 此外，传统的CMOS BEOL Cu互连技术应用于中间互连级别和全局互连级别。 以这种方式，可以有效地克服当局部互连尺寸相对较小时可能发生的Cu互连技术中的高寄生电阻和寄生电容。

公开(公告)号：US09305951B2

公开(公告)日：2016-04-05

申请号：US14439229

申请日：2012-12-28

申请人： Xiaoxu Kang ,  Yuhang Zhao

发明人： Xiaoxu Kang ,  Yuhang Zhao

IPC分类号： H01L27/146

CPC分类号： H01L27/14623 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/14629 ,  H01L27/14636 ,  H01L27/14645 ,  H01L27/14685 ,  H01L27/14689

摘要： A pixel structure of a CMOS image sensor pixel structure and a manufacturing method thereof. The structure comprises a photosensitive element (37) and a multi-layer structure of a standard CMOS device arranged on the silicon substrate (31). A deep groove (38) having a light-transmitting space therein is formed above the photosensitive element, a side wall of the deep groove is surrounded by a light reflection shielding layer (39) continuously arranged in a longitudinal direction to reflect the light incident on the light reflection shielding layer. The side wall of the deep groove is surrounded by metal interconnects, vias, contact holes and polysilicon in annular configurations, thus the incident light on the deep grove is substantially completely reflected, which avoids the optical crosstalk and effectively improves the optical resolution and sensitivity of the pixel and the performance and reliability of the chip.

摘要翻译： CMOS图像传感器像素结构的像素结构及其制造方法。 该结构包括光敏元件（37）和布置在硅衬底（31）上的标准CMOS器件的多层结构。 在感光元件的上方形成有具有透光空间的深槽（38），深槽的侧壁由沿纵向方向连续排列的光反射屏蔽层（39）包围，以反射入射到 光反射屏蔽层。 深槽的侧壁由金属互连，通孔，接触孔和环状构造的多晶硅围绕，因此深沟槽中的入射光基本上完全反射，从而避免了光学串扰，并有效提高了光学分辨率和灵敏度 像素和芯片的性能和可靠性。

公开(公告)号：US09269613B2

公开(公告)日：2016-02-23

申请号：US14125314

申请日：2011-12-20

申请人： Yuhang Zhao ,  Xiaoxu Kang

发明人： Yuhang Zhao ,  Xiaoxu Kang

IPC分类号： H01L21/768 ,  H01L23/532 ,  H01L23/528

CPC分类号： H01L21/7682 ,  H01L21/76804 ,  H01L21/76807 ,  H01L23/528 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method is disclosed for manufacturing a semiconductor device with a copper interconnect structure. The method includes providing a substrate, forming a first interconnect dielectric layer on the substrate, and forming a second interconnect dielectric layer on a surface of the first interconnect dielectric layer. The method also includes forming a plurality of conduits extending through the first interconnect dielectric layer and the second interconnect dielectric layer, and depositing copper in the plurality of conduits to form a copper interconnect layer of the copper interconnect structure. Further, the first interconnect dielectric layer, between neighboring conduits, contains cavities such that dielectric constant of the first interconnect dielectric layer is reduced. The second interconnect dielectric layer seals the top of the cavities, the substrate is the bottom of the cavities, and a width of the top of the cavities is less than a width of the bottom of the cavities.

摘要翻译： 公开了一种用于制造具有铜互连结构的半导体器件的方法。 该方法包括提供衬底，在衬底上形成第一互连电介质层，以及在第一互连电介质层的表面上形成第二互连电介质层。 该方法还包括形成延伸穿过第一互连电介质层和第二互连电介质层的多个导管，以及在多个导管中沉积铜以形成铜互连结构的铜互连层。 此外，相邻导管之间的第一互连电介质层包含空腔，使得第一互连电介质层的介电常数降低。 第二互连电介质层密封空腔的顶部，衬底是空腔的底部，并且空腔的顶部的宽度小于腔的底部的宽度。

公开(公告)号：US20140138829A1

公开(公告)日：2014-05-22

申请号：US14125313

申请日：2011-12-31

申请人： Yuhang Zhao ,  Xiaoxu Kang

发明人： Yuhang Zhao ,  Xiaoxu Kang

IPC分类号： H01L23/532 ,  H01L21/285 ,  H01L21/768

CPC分类号： H01L23/53276 ,  H01L21/28562 ,  H01L21/76801 ,  H01L21/7682 ,  H01L21/76838 ,  H01L21/7684 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76895 ,  H01L23/5222 ,  H01L23/53295 ,  H01L2221/1094 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention relates to an interconnection structure and a method for fabricating the same. According to the present invention, cavities are formed between the interconnection dielectric by using a sacrificial layer, carbon nanotubes are used as the interconnection material for local interconnection between via holes, graphene nanoribbons are used as the interconnection material for metal lines, and cavities are included in the interconnection dielectric. In addition, the conventional CMOS BEOL Cu interconnection technique is applied to the intermediate interconnection level and the global interconnection level. In this way, the high parasitic resistance and parasitic capacitance in the Cu interconnection technique, which may occur when the local interconnection is relatively small in size, can be effectively overcome.

摘要翻译： 互连结构及其制造方法技术领域本发明涉及互连结构及其制造方法。 根据本发明，通过使用牺牲层在互连电介质之间形成空腔，碳纳米管用作用于通孔之间的局部互连的互连材料，石墨烯纳米带用作金属线的互连材料，并且包括空腔 在互连电介质中。 此外，传统的CMOS BEOL Cu互连技术应用于中间互连级别和全局互连级别。 以这种方式，可以有效地克服当局部互连尺寸相对较小时可能发生的Cu互连技术中的高寄生电阻和寄生电容。

公开(公告)号：US20140138835A1

公开(公告)日：2014-05-22

申请号：US14125314

申请日：2011-12-20

申请人： Yuhang Zhao ,  Xiaoxu Kang

发明人： Yuhang Zhao ,  Xiaoxu Kang

IPC分类号： H01L21/768 ,  H01L23/528

CPC分类号： H01L21/7682 ,  H01L21/76804 ,  H01L21/76807 ,  H01L23/528 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method is disclosed for manufacturing a semiconductor device with a copper interconnect structure. The method includes providing a substrate, forming a first interconnect dielectric layer on the substrate, and forming a second interconnect dielectric layer on a surface of the first interconnect dielectric layer. The method also includes forming a plurality of conduits extending through the first interconnect dielectric layer and the second interconnect dielectric layer, and depositing copper in the plurality of conduits to form a copper interconnect layer of the copper interconnect structure. Further, the first interconnect dielectric layer, between neighboring conduits, contains cavities such that dielectric constant of the first interconnect dielectric layer is reduced. The second interconnect dielectric layer seals the top of the cavities, the substrate is the bottom of the cavities, and a width of the top of the cavities is less than a width of the bottom of the cavities.

摘要翻译： 公开了一种用于制造具有铜互连结构的半导体器件的方法。 该方法包括提供衬底，在衬底上形成第一互连电介质层，以及在第一互连电介质层的表面上形成第二互连电介质层。 该方法还包括形成延伸穿过第一互连电介质层和第二互连电介质层的多个导管，以及在多个导管中沉积铜以形成铜互连结构的铜互连层。 此外，相邻导管之间的第一互连电介质层包含空腔，使得第一互连电介质层的介电常数降低。 第二互连电介质层密封空腔的顶部，衬底是空腔的底部，并且空腔的顶部的宽度小于腔的底部的宽度。

公开(公告)号：US08193057B2

公开(公告)日：2012-06-05

申请号：US12946162

申请日：2010-11-15

申请人： Xiaoxu Kang

发明人： Xiaoxu Kang

IPC分类号： H01L21/336

CPC分类号： H01L29/7833 ,  H01L29/1083 ,  H01L29/665 ,  H01L29/66621 ,  H01L29/7834

摘要： The invention is related to a MOS transistor and its fabrication method to reduce short-channel effects. Existing process has the problem of high complexity and high cost to reduce short-channel effects by using epitaxial technique to produce an elevated source and drain structure. In the invention, the MOS transistor, fabricated on a silicon substrate after an isolation module is finished, includes a gate stack, a gate sidewall spacer, and source and drain areas. The silicon substrate has a groove and the gate stack is formed in the groove. And the process for the MOS transistor includes the following steps: forming the groove; carrying out well implantation, anti-punchthrough implantation and threshold-voltage adjustment implantation; forming the gate stack in the groove which comprising patterning the gate electrode; carrying lightly doped drain implantation and halo implantation; forming the gate sidewall spacer; carrying source and drain implantation to get the source and drain areas; forming a metal silicide layer on the source and drain areas.

摘要翻译： 本发明涉及一种降低短沟道效应的MOS晶体管及其制造方法。 现有的方法具有高复杂性和高成本的问题，以通过使用外延技术来产生升高的源极和漏极结构来减少短沟道效应。 在本发明中，在隔离模块完成之后在硅衬底上制造的MOS晶体管包括栅极堆叠，栅极侧壁间隔物以及源极和漏极区域。 硅衬底具有沟槽，并且栅极堆叠形成在沟槽中。 并且MOS晶体管的工艺包括以下步骤：形成凹槽; 进行良好的注入，抗穿透植入和阈值电压调整植入; 在所述槽中形成所述栅极堆叠，其包括图案化所述栅电极; 携带轻掺杂漏极注入和晕圈注入; 形成栅极侧壁间隔物; 承载源极和漏极植入以获得源极和漏极区域; 在源极和漏极区域上形成金属硅化物层。

公开(公告)号：US09368565B2

公开(公告)日：2016-06-14

申请号：US13884970

申请日：2012-02-07

申请人： Qingyun Zuo ,  Xiaoxu Kang ,  Shaohai Zeng

发明人： Qingyun Zuo ,  Xiaoxu Kang ,  Shaohai Zeng

IPC分类号： H01L21/33 ,  H01L21/00 ,  H01L49/02 ,  H01L23/522 ,  H01L23/532

CPC分类号： H01L28/20 ,  H01L23/5228 ,  H01L23/53238 ,  H01L28/24 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method is provided for manufacturing a semiconductor device with a metal film resistor structure. The method includes providing an insulation layer on the semiconductor device. A lower copper interconnect is formed in the insulation layer. The method also includes forming a cap layer on the insulation layer and the lower copper interconnect and etching the cap layer based on a single photolithography mask to form a window exposing portion of the lower copper interconnect and portion of the insulation layer. Further, the method includes forming a metal film layer on the cap layer and inside the window such that exposed portion of the lower copper interconnect is connected with part of the metal film layer within the window. The method also includes performing a chemical mechanical polishing (CMP) process to form a metal film resistor based on the metal film layer. The metal film resistor is connected with the portion of the lower copper interconnect.

摘要翻译： 提供一种用于制造具有金属膜电阻器结构的半导体器件的方法。 该方法包括在半导体器件上提供绝缘层。 在绝缘层中形成较低的铜互连。 该方法还包括在绝缘层和下铜互连上形成覆盖层，并且基于单个光刻掩模蚀刻覆盖层以形成下铜互连和绝缘层的一部分的窗口暴露部分。 此外，该方法包括在盖层和窗内部形成金属膜层，使得下铜互连的暴露部分与窗内的金属膜层的一部分连接。 该方法还包括进行化学机械抛光（CMP）工艺以形成基于金属膜层的金属膜电阻器。 金属膜电阻器与下部铜互连部分连接。

公开(公告)号：US20140217550A1

公开(公告)日：2014-08-07

申请号：US13884970

申请日：2012-02-07

申请人： Qingyun Zuo ,  Xiaoxu Kang ,  Shaohai Zeng

发明人： Qingyun Zuo ,  Xiaoxu Kang ,  Shaohai Zeng

IPC分类号： H01L49/02

CPC分类号： H01L28/20 ,  H01L23/5228 ,  H01L23/53238 ,  H01L28/24 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method is provided for manufacturing a semiconductor device with a metal film resistor structure. The method includes providing an insulation layer on the semiconductor device. A lower copper interconnect is formed in the insulation layer. The method also includes forming a cap layer on the insulation layer and the lower copper interconnect and etching the cap layer based on a single photolithography mask to form a window exposing portion of the lower copper interconnect and portion of the insulation layer. Further, the method includes forming a metal film layer on the cap layer and inside the window such that exposed portion of the lower copper interconnect is connected with part of the metal film layer within the window. The method also includes performing a chemical mechanical polishing (CMP) process to form a metal film resistor based on the metal film layer. The metal film resistor is connected with the portion of the lower copper interconnect.

摘要翻译： 提供一种用于制造具有金属膜电阻器结构的半导体器件的方法。 该方法包括在半导体器件上提供绝缘层。 在绝缘层中形成较低的铜互连。 该方法还包括在绝缘层和下铜互连上形成覆盖层，并且基于单个光刻掩模蚀刻覆盖层以形成下铜互连和绝缘层的一部分的窗口暴露部分。 此外，该方法包括在盖层和窗内部形成金属膜层，使得下铜互连的暴露部分与窗内的金属膜层的一部分连接。 该方法还包括进行化学机械抛光（CMP）工艺以形成基于金属膜层的金属膜电阻器。 金属膜电阻器与下部铜互连部分连接。