OUTPUTTING OF CODEWORD BITS FOR TRANSMISSION PRIOR TO LOADING ALL INPUT BITS

    公开(公告)号:US20180048334A1

    公开(公告)日:2018-02-15

    申请号:US15616792

    申请日:2017-06-07

    Abstract: Methods, systems, and devices for outputting of codeword bits for transmission prior to loading all input bits. An example encoder may have multiple encoding branches. The encoder may divide the encoding branches into first and second encoding branch subsets, outputs of the first encoding branch subset being independent of inputs to the second encoding branch subset. The encoder may generate first and second subsets of output bits of a codeword in first and second encoding operations, the generating comprising inputting information bits of an information bit-vector and at least one frozen bit into respective encoding branches of the plurality of encoding branches and generating the first subset of output bits using the first encoding branch subset prior to generating the second subset of output bits using the second encoding branch subset. The encoder may output the first subset of output bits prior to outputting the second subset of output bits.

    ENHANCED LVA DECODING USING ITERATIVE COMPARISON TRELLIS CONSTRUCTION

    公开(公告)号:US20170359146A1

    公开(公告)日:2017-12-14

    申请号:US15592519

    申请日:2017-05-11

    CPC classification number: H04L1/0054 H03M13/4115 H04L1/005

    Abstract: The described techniques relate to improved methods, systems, devices, or apparatuses that support enhanced efficiency in list Viterbi algorithm (LVA) decoding using iterative comparison trellis construction. Iterative comparison may involve comparison and selection from ordered accumulated path metrics associated with feeding transitions by selecting, for each successive rank of an ordered path metrics list for the current stage, the best unselected accumulated path metric of the feeding transitions. The iterative comparison may be performed sequentially for each stage before processing the next stage. Alternatively, the iterative comparison may be pipelined across stages, and different ranks of the ordered path metrics lists for different stages may be concurrently computed in a single trellis search cycle using multiple comparators. Iterative comparison may be used in an inner decoder to generate an ordered path metrics list for processing according to an error checking function using an outer decoder.

    MODULATION ORDER SPLIT TRANSMISSIONS USING A UNIFORM CONSTELLATION

    公开(公告)号:US20170331662A1

    公开(公告)日:2017-11-16

    申请号:US15426883

    申请日:2017-02-07

    Abstract: A combined symbol constellation may be selected from a uniform symbol constellation that is supported by a de-mapper to provide additional power split options while reducing modifications to the de-mapper. In some examples, a signal may be constructed according to a combined symbol constellation selected from a larger uniform symbol constellation based on a desired power-ratio. The signal may include a base-layer, used to communicate a first set of data, and an enhancement-layer, used to communicate a second set of data, in accordance with the selected combined symbol constellation. The signal may be received and de-mapped according to the combined symbol constellation at a de-mapper that supports a uniform symbol constellation that is larger than the combined symbol constellation.

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