-
221.发明申请BIT INTERLEAVER FOR LOW-DENSITY PARITY CHECK CODEWORD HAVING LENGTH OF 64800 AND CODE RATE OF 5/15 AND 64-SYMBOL MAPPING, AND BIT INTERLEAVING METHOD USING SAME 有权用于低密度奇偶校验的位交换机检查长度为64800，编码速率为5/15和64符号映射，以及使用相同的位交互方法公开(公告)号：US20150236720A1
公开(公告)日：2015-08-20
申请号：US14625550
申请日：2015-02-18
Inventor： Sung-Ik PARK , Sun-Hyoung KWON , Jae-Young LEE , Heung-Mook KIM , Nam-Ho HUR
CPC classification number: H03M13/2792 , H03M13/1148 , H03M13/116 , H03M13/1185 , H03M13/255 , H03M13/2778 , H04L1/0041 , H04L1/0045 , H04L1/0058 , H04L1/0071
Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 5/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 64-symbol mapping.
Abstract translation: 本文公开了一种位交织器，位交织编码调制（BICM）装置和比特交织方法。 比特交织器包括第一存储器，处理器和第二存储器。 第一存储器存储长度为64800且码率为5/15的低密度奇偶校验（LDPC）码字。 处理器通过基于比特组交织LDPC码字来产生交错码字。 位组的大小对应于LDPC码字的并行因子。 第二存储器将交织的码字提供给用于64符号映射的调制器。
-
222.发明申请MODULATOR AND MODULATION METHOD USING NON-UNIFORM 16-SYMBOL SIGNAL CONSTELLATION FOR LOW-DENSITY PARITY CHECK CODEWORD HAVING 4/15 CODE RATE 有权使用非均匀16符号信号的调制解调器和调制方法用于低密度奇偶校验检查具有4/15码率的编码公开(公告)号：US20150229336A1
公开(公告)日：2015-08-13
申请号：US14620682
申请日：2015-02-12
Inventor： Sung-Ik PARK , Sun-Hyoung KWON , Jae-Young LEE , Heung-Mook KIM , Nam-Ho HUR
CPC classification number: H03M13/2792 , H03M13/1165 , H03M13/255 , H03M13/616 , H03M13/6552 , H04L1/0041 , H04L1/0042 , H04L1/0057 , H04L1/0071 , H04L27/3422
Abstract: A modulator and a modulation method using a non-uniform 16-symbol signal constellation are disclosed. The modulator includes a memory and a processor. The memory receives a codeword corresponding to a low-density parity check (LDPC) code having a code rate of 4/15. The processor maps the codeword to 16 symbols of the non-uniform 16-symbol signal constellation on a 4-bit basis.
Abstract translation: 公开了一种使用非均匀16符号信号星座的调制器和调制方法。 调制器包括存储器和处理器。 存储器接收与码率为4/15的低密度奇偶校验（LDPC）码对应的码字。 处理器将码字映射为4比特的16位符号的不均匀16符号信号星座。
-
223.发明申请MODULATOR AND MODULATION METHOD USING NON-UNIFORM 16-SYMBOL SIGNAL CONSTELLATION FOR LOW-DENSITY PARITY CHECK CODEWORD HAVING 7/15 CODE RATE 审中-公开使用非均匀16符号信号的调制解调器和调制方法用于低密度奇偶校验检查具有7/15代码率的编码公开(公告)号：US20150229334A1
公开(公告)日：2015-08-13
申请号：US14618952
申请日：2015-02-10
Inventor： Sung-Ik PARK , Sun-Hyoung KWON , Jae-Young LEE , Heung-Mook KIM , Nam-Ho HUR
CPC classification number: H03M13/2792 , H03M13/1165 , H03M13/255 , H03M13/27 , H03M13/616 , H03M13/6552 , H04L1/0041 , H04L1/0042 , H04L1/0057 , H04L1/0071 , H04L27/3405
Abstract: A modulator and a modulation method using a non-uniform 16-symbol signal constellation are disclosed. The modulator includes a memory and a processor. The memory receives a codeword corresponding to a low-density parity check (LDPC) code having a code rate of 7/15. The processor maps the codeword to 16 symbols of the non-uniform 16-symbol signal constellation on a 4-bit basis.
Abstract translation: 公开了一种使用非均匀16符号信号星座的调制器和调制方法。 调制器包括存储器和处理器。 存储器接收与码率为7/15的低密度奇偶校验（LDPC）码对应的码字。 处理器将码字映射为4比特的16位符号的不均匀16符号信号星座。
-
224.发明申请BIT INTERLEAVER FOR LOW-DENSITY PARITY CHECK CODEWORD HAVING LENGTH OF 64800 AND CODE RATE OF 7/15 AND QUADRATURE PHASE SHIFT KEYING, AND BIT INTERLEAVING METHOD USING SAME 有权用于低密度奇偶校验的位交换机检查长度为64800的长度和7/15的编码速率和相位相移键控和使用相同的位交互方法公开(公告)号：US20150214982A1
公开(公告)日：2015-07-30
申请号：US14606949
申请日：2015-01-27
Inventor： Sung-Ik PARK , Sun-Hyoung KWON , Jae-Young LEE , Heung-Mook KIM , Nam-Ho HUR
CPC classification number: H03M13/2792 , H03M13/1102 , H03M13/116 , H03M13/1185 , H03M13/255 , H03M13/2757 , H03M13/2778 , H03M13/616 , H03M13/6552 , H04L1/0041 , H04L1/0057 , H04L1/0058 , H04L1/0071 , H04L27/20 , H04L27/3416
Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 7/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for quadrature phase shift keying (QPSK) modulation.
Abstract translation: 本文公开了一种位交织器，位交织编码调制（BICM）装置和比特交织方法。 比特交织器包括第一存储器，处理器和第二存储器。 第一存储器存储长度为64800且码率为7/15的低密度奇偶校验（LDPC）码字。 处理器通过基于比特组交织LDPC码字来产生交错码字。 位组的大小对应于LDPC码字的并行因子。 第二存储器将交织的码字提供给用于正交相移键控（QPSK）调制的调制器。
-
225.发明公开公开(公告)号：US20240162918A1
公开(公告)日：2024-05-16
申请号：US18419393
申请日：2024-01-22
Inventor： Sung-Ik PARK , Heung-Mook KIM , Sun-Hyoung KWON , Nam-Ho HUR
CPC classification number: H03M13/1157 , H03M13/1165 , H03M13/1177 , H03M13/616 , H03M13/618
Abstract: A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 64800 and a code rate of 7/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).
-
Patent Agency Ranking
226.发明公开公开(公告)号：US20240155165A1
公开(公告)日：2024-05-09
申请号：US18242775
申请日：2023-09-06
Inventor： Hyun-Jeong YIM , Sung-Ik PARK , Bo-Mi LIM
IPC: H04N21/235 , H04N21/643
CPC classification number: H04N21/235 , H04N21/643
Abstract: Disclosed herein are a method and apparatus for transmitting an 8K Scalable High Efficiency Video Coding (SHVC) service based on broadcast network interconnection. The method includes defining signaling information for the 8K SHVC service, and delivering the defined signaling information to a MPEG Media Transport (MMT)/Real time Object delivery Over Unidirectional Transport (ROUTE) packetizer or to a gateway, separating 8K content into a base layer compatible with a broadcast network and an enhancement layer compatible with a communication network, delivering the base layer from the MMT/ROUTE packetizer to a receiver through the gateway and a transmitter, and delivering the enhancement layer to the receiver through a Dynamic Adaptive Streaming over HTTP (DASH) server.
-
227.发明公开公开(公告)号：US20230371048A1
公开(公告)日：2023-11-16
申请号：US18354251
申请日：2023-07-18
Inventor： Jae-Young LEE , Soon-Choul KIM , Sung-Ik PARK , Heung-Mook KIM
CPC classification number: H04W72/30 , H04L12/1859 , H04L12/4633
Abstract: Disclosed herein are a method and apparatus of broadcast gateway signaling for channel bonding. The apparatus for broadcast gateway signaling includes an input formatting unit configured to generate baseband packets corresponding to channel bonding; and a stream partitioner configured to allocate the baseband packets to two or more RF channels of the channel bonding for generating an outer tunnel data stream, the outer tunnel data stream generated in different ways according to a plurality of operation modes for the channel bonding.
-
公开(公告)号：US20230268935A1
公开(公告)日：2023-08-24
申请号：US18309278
申请日：2023-04-28
Inventor： Sung-Ik PARK , Sun-Hyoung KWON , Jae-Young LEE , Heung-Mook KIM , Nam-Ho HUR
CPC classification number: H03M13/2757 , H04L27/20 , H03M13/2792 , H04L27/3416 , H03M13/255 , H04L1/0057 , H04L1/0071 , H03M13/116 , H03M13/1185 , H03M13/2778 , H03M13/1102 , H03M13/616 , H03M13/6552 , H04L1/0041 , H04L1/0058
Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 7/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for quadrature phase shift keying (QPSK) modulation.
-
229.发明公开公开(公告)号：US20230155634A1
公开(公告)日：2023-05-18
申请号：US17859969
申请日：2022-07-07
Inventor： Bo-Mi LIM , Hoi-Yoon JUNG , Sung-Ik PARK , Hae-Chan KWON , Sung-Jun AHN , Nam-Ho HUR , Hyun-Jeong YIM
IPC: H04B7/0413 , H04W4/06 , H04L1/00
CPC classification number: H04B7/0413 , H04W4/06 , H04L1/0071
Abstract: Disclosed herein are a method for transmitting a broadcast signal for signaling information about a combination of Layered-Division Multiplexing (LDM) technology and Multiple-Input Multiple-Output (MIMO) technology and an apparatus using the method. The method includes generating first signaling information indicating whether MIMO technology is applied to an enhanced layer by LDM technology, generating second signaling information indicating an MIMO application method when the MIMO technology is applied to the enhanced layer, and generating a broadcast signal using the first signaling information and the second signaling information.
-
公开(公告)号：US20230022090A1
公开(公告)日：2023-01-26
申请号：US17780446
申请日：2020-11-24
Inventor： Sung-Ik PARK , Sun-Hyoung KWON , Jae-Young LEE
Abstract: An apparatus for transmitting a broadcast signal according to an embodiment of the present invention includes a bootstrap generation unit for generating a bootstrap for signaling a system bandwidth field, corresponding to a system bandwidth for a post-bootstrap, and a baseband sampling rate coefficient; a preamble generation unit for generating a preamble located immediately following the bootstrap in a broadcast signal frame; and a payload generation unit for generating one or more subframes located immediately following the preamble in the broadcast signal frame.
-
-
-
-
-
-
-
-
-
Search Results
283
records
(took 0.031 seconds)
