公开(公告)号：US11923857B1

公开(公告)日：2024-03-05

申请号：US18102066

申请日：2023-01-26

Applicant: XILINX, INC.

Inventor： Hongtao Zhang ,  Ankur Jain ,  Yanfei Chen ,  Ronan Sean Casey ,  Winson Lin ,  Hsung Jai Im

IPC: H03L7/08 ,  H03L7/099 ,  H03M1/82

CPC classification number: H03L7/0802 ,  H03L7/0991 ,  H03M1/82

Abstract: Embodiments herein describe correcting nonlinearity in a Digital-to-Time Converter (DTC) by relaxing a DTC linearity requirement, which results in the correction being co-adapted with a DTC gain calibration loop which can operate in parallel with a DTC integral nonlinearity (INL) correction loop. In one embodiment, the DTC gain calibration loop and the DTC INL correction loop are constrained when determining a nonlinearity correction code to improve the likelihood they converge. Once determined, the nonlinearity correction code can be combined with an digital code output by a time-to-digital converter (TDC) to generate a phase difference between a reference clock and a feedback clock.

公开(公告)号：US10985764B1

公开(公告)日：2021-04-20

申请号：US16918854

申请日：2020-07-01

Applicant: XILINX, INC.

Inventor： Winson Lin ,  Jin Namkoong ,  Hongtao Zhang

IPC: H04L7/00 ,  H04L7/033 ,  H04L25/03 ,  H03L7/087 ,  H03L7/08

Abstract: An example method of clock and data recovery (CDR) includes adding a pre-defined offset to an output of a phase detector (PD) of a CDR circuit, and loading an accumulator of a frequency loop of the CDR circuit with a pre-defined load value. The method further includes detecting the phase of an incoming signal using a PD, and determining that the CDR has locked onto a real lock point. In some examples, the method further includes determining that the CDR has locked on a real lock point, and, in response to the determination, modifying the pre-defined offset to equal zero.

公开(公告)号：US09960902B1

公开(公告)日：2018-05-01

申请号：US15380653

申请日：2016-12-15

Applicant: Xilinx, Inc.

Inventor： Winson Lin ,  Yu Xu ,  Caleb S. Leung ,  Alan C. Wong ,  Christopher J. Borrelli ,  Yohan Frans ,  Kun-Yung Chang

IPC: H04L7/00 ,  H04L1/20

CPC classification number: H04L1/205 ,  H03L7/0814 ,  H04L7/0037 ,  H04L7/033 ,  H04L7/0337

Abstract: An example method of clock and data recovery in a receiver includes generating data samples and crossing samples of a received signal based on a data clock signal and a crossing clock signal, respectively, which are derived from a sampling clock signal; adjusting a phase of the sampling clock signal using a clock and data recovery (CDR) circuit based on the data samples and the crossing samples; adjusting relative phase between the data clock signal and the crossing clock signal from a first phase difference to a second phase difference that is less than ninety degrees; and reverting the relative phase between the data clock signal and the crossing clock signal to the first phase difference after a threshold time period.

公开(公告)号：US09882703B1

公开(公告)日：2018-01-30

申请号：US15346434

申请日：2016-11-08

Applicant: Xilinx, Inc.

Inventor： Yu Xu ,  Winson Lin ,  Caleb S. Leung ,  Alan C. Wong ,  Christopher J. Borrelli ,  Yohan Frans ,  Kun-Yung Chang

IPC: H03D3/24 ,  H04L7/00 ,  H04L12/26 ,  H04L7/033

CPC classification number: H04L43/16 ,  H04L7/0025 ,  H04L7/0083 ,  H04L7/033 ,  H04L25/03 ,  H04L43/028

Abstract: An example method of clock and data recovery in a receiver includes generating data samples and crossing samples of a received signal based on a data phase and a crossing phase, respectively, of a sampling clock supplied by a phase interpolator in the receiver; generating a phase detect result signal in response to phase detection of the data samples and the crossing samples; filtering the phase detect result signal to generate a phase interpolator code, the phase interpolator generating the sampling clock based on the phase interpolator code; determining an average phase detect result from the phase detect result signal; and adjusting the phase interpolator code in response to the average phase detect result being less than a threshold value.