公开(公告)号：US20170161419A1

公开(公告)日：2017-06-08

申请号：US14960176

申请日：2015-12-04

Applicant: Xilinx, Inc.

Inventor： Ilya K. Ganusov ,  Henri Fraisse ,  Ashish Sirasao ,  Alireza S. Kaviani

IPC: G06F17/50

CPC classification number: G06F17/5072 ,  G06F17/5045 ,  G06F17/505 ,  G06F17/5054

Abstract: Disclosed approaches for processing a circuit design include identifying duplicate instances of a module in a representation of the circuit design. A processor circuit performs folding operations for at least one pair of the duplicate instances of the module. One instance of the duplicates is removed from the circuit design, and a multiplexer is inserted. The multiplexer receives and selects one of the input signals to the duplicate instances and provides the selected input signal to the remaining instance. For each flip-flop in the remaining instance, a pipelined flip-flop is inserted. Connections to a first clock signal in the remaining instance are replaced with connections to a second clock signal having twice the frequency of the first clock signal. An alignment circuit is inserted to receive the output signal from the first instance and provide concurrent first and second output signals.

公开(公告)号：US11138019B1

公开(公告)日：2021-10-05

申请号：US16420935

申请日：2019-05-23

Applicant: Xilinx, Inc.

Inventor： Akella Sastry ,  Henri Fraisse ,  Rishi Surendran ,  Abnikant Singh

IPC: G06F9/445 ,  G06F13/40 ,  G06F16/901 ,  G06F13/28

Abstract: An example method of implementing an application for a system-on-chip (SOC) having a data processing engine (DPE) array including determining a graph representation of the application, the graph representation including nodes representing kernels of the application and edges representing communication between the kernels, mapping, based on the graph, the kernels onto DPEs of the DPE array and data structures of the kernels onto memory in the DPE array, building a routing graph of all possible routing choices in the DPE array for communicate channels between DPEs and circuitry of the application configured in programmable logic of the SOC, adding constraints to the routing graph based on an architecture of the DPE array, routing communication channels between DPEs and circuitry of the application configured in programmable logic of the SOC based on the routing graph, and generating implementation data for programming the SOC to implement the application based on results of the mapping and the routing.

公开(公告)号：US09954534B2

公开(公告)日：2018-04-24

申请号：US15267880

申请日：2016-09-16

Applicant: Xilinx, Inc.

Inventor： Ilya K. Ganusov ,  Benjamin S. Devlin ,  Henri Fraisse

IPC: H03K19/177 ,  H01L25/00 ,  H03K3/037 ,  G06F17/50

CPC classification number: H03K19/1776 ,  G06F17/5072 ,  G06F17/5077 ,  H03K3/0372 ,  H03K3/0375 ,  H03K19/17728

Abstract: Aspects of various embodiments of the present disclosure are directed to methods and circuits for preventing hold time violations in clock synchronized circuits. In an example implementation, a circuit includes at least a first flip-flop, a second flip-flop, and a level-sensitive latch connected in a signal path from the first flip-flop to the second flip-flop. A clock node of the first flip-flop is connected to receive a first clock signal and a clock node of the second flip-flop is connected to receive a second clock signal. The propagation delay from the first flip-flop through the level-sensitive latch to the second flip-flop is smaller than the skew between the first clock and the second clock, thereby presenting a hold time violation. A level-sensitive latch control circuit is configured to prevent the hold time violation by providing a pulsed clock signal to a clock node of the one level-sensitive latch circuit.

公开(公告)号：US09935870B2

公开(公告)日：2018-04-03

申请号：US14995839

申请日：2016-01-14

Applicant: Xilinx, Inc.

Inventor： Henri Fraisse

IPC: H04L12/701 ,  H04L12/707 ,  H04L12/761 ,  H04L12/933

CPC classification number: H04L45/24 ,  H04L45/16 ,  H04L49/101 ,  H04L49/15 ,  H04L49/253

Abstract: Methods and systems are disclosed for selecting channels for routing signals in a multi-channel switching network. In an example implementation, pairs of the signals that can be routed together over one channel in the multi-channel switching network are determined. A model graph is generated that has a respective vertex for each of the signals. The model graph also includes respective edges for the determined pairs connecting vertices corresponding to signals of the pair. A subset of the edges that includes a maximum number of disjoint edges is determined. Pairs of signals represented by the respective vertices connected by the edge are routed over a respective one of the channels. For vertices not connected to an edge in the subset, the signals represented by the vertices are routed via a respective one of the channels.

公开(公告)号：US20180083633A1

公开(公告)日：2018-03-22

申请号：US15267880

申请日：2016-09-16

Applicant: Xilinx, Inc.

Inventor： Ilya K. Ganusov ,  Benjamin S. Devlin ,  Henri Fraisse

IPC: H03K19/177 ,  H03K3/037 ,  G06F17/50

CPC classification number: H03K19/1776 ,  G06F17/5072 ,  G06F17/5077 ,  H03K3/0372 ,  H03K3/0375 ,  H03K19/17728

Abstract: Aspects of various embodiments of the present disclosure are directed to methods and circuits for preventing hold time violations in clock synchronized circuits. In an example implementation, a circuit includes at least a first flip-flop, a second flip-flop, and a level-sensitive latch connected in a signal path from the first flip-flop to the second flip-flop. A clock node of the first flip-flop is connected to receive a first clock signal and a clock node of the second flip-flop is connected to receive a second clock signal. The propagation delay from the first flip-flop through the level-sensitive latch to the second flip-flop is smaller than the skew between the first clock and the second clock, thereby presenting a hold time violation. A level-sensitive latch control circuit is configured to prevent the hold time violation by providing a pulsed clock signal to a clock node of the one level-sensitive latch circuit.

公开(公告)号：US09882562B1

公开(公告)日：2018-01-30

申请号：US15371472

申请日：2016-12-07

Applicant: Xilinx, Inc.

Inventor： Martin L. Voogel ,  Rafael C. Camarota ,  Henri Fraisse

IPC: H03K19/177 ,  H03K19/00 ,  H01L23/498

CPC classification number: H03K19/0008 ,  H01L23/49811 ,  H01L23/49838 ,  H03K19/17728 ,  H03K19/17744

Abstract: An integrated circuit (IC) die and integrated circuit (IC) chip packages having such dies are described that leverage the symmetry of the arrangement of micro-bumps to advantageously reduce interposer cost and size requirements. In one example, an integrated circuit (IC) die is provided. The IC die includes a die body, a plurality of programmable tiles disposed in the die body, and a plurality of micro-bumps disposed in the die body. The die body includes a front face connecting a bottom exterior surface and a top exterior surface. A centerline of the die body is perpendicular to the front face and bifurcates the top exterior surface. At least two of the programmable tiles are of a common type. The micro-bumps adjacent the front face and coupled to the common type of programmable tiles have a substantially symmetrical orientation relative to a symmetry axis. The symmetry axis being one of (a) collinear with the centerline of the die body, or (b) parallel to the centerline of the die body.