公开(公告)号：US11138019B1

公开(公告)日：2021-10-05

申请号：US16420935

申请日：2019-05-23

Applicant: Xilinx, Inc.

Inventor： Akella Sastry ,  Henri Fraisse ,  Rishi Surendran ,  Abnikant Singh

IPC: G06F9/445 ,  G06F13/40 ,  G06F16/901 ,  G06F13/28

Abstract: An example method of implementing an application for a system-on-chip (SOC) having a data processing engine (DPE) array including determining a graph representation of the application, the graph representation including nodes representing kernels of the application and edges representing communication between the kernels, mapping, based on the graph, the kernels onto DPEs of the DPE array and data structures of the kernels onto memory in the DPE array, building a routing graph of all possible routing choices in the DPE array for communicate channels between DPEs and circuitry of the application configured in programmable logic of the SOC, adding constraints to the routing graph based on an architecture of the DPE array, routing communication channels between DPEs and circuitry of the application configured in programmable logic of the SOC based on the routing graph, and generating implementation data for programming the SOC to implement the application based on results of the mapping and the routing.

公开(公告)号：US11615052B1

公开(公告)日：2023-03-28

申请号：US16420946

申请日：2019-05-23

Applicant: Xilinx, Inc.

Inventor： Rishi Surendran ,  Akella Sastry ,  Abnikant Singh

IPC: G06F15/78 ,  G06F16/901 ,  G06F30/20 ,  H04L49/109 ,  H04L49/25

Abstract: Some examples described herein relate to packet identification (ID) assignment for a routing network in a programmable integrated circuit (IC). In an example, a design system includes a processor and a memory coupled to the processor. The memory stores instruction code. The processor is configured to execute the instruction code to construct an interference graph based on routes of logical nets through switches in a routing network, and assign identifications to the routes comprising performing vertex coloring of vertices of the interference graph. The interference graph includes the vertices and interference edges. Each vertex represents one of the logical nets having a route. Each interference edge connects two vertices that represent corresponding two logical nets that have routes that share at least one port of a switch. The identifications correspond to values assigned to the vertices by the vertex coloring.

公开(公告)号：US12086576B2

公开(公告)日：2024-09-10

申请号：US17877395

申请日：2022-07-29

Applicant: XILINX, INC.

Inventor： Abnikant Singh

IPC: G06F9/44 ,  G06F8/41

CPC classification number: G06F8/443 ,  G06F8/41

Abstract: A multi-core architecture in some examples may have hundreds of “cores”, each core comprising a digital signal processor (DSP) and various functional computing units. A method of implementing a multi-core graph compiler for a system-on-chip (SOC) having a data processing engine (DPE) array is disclosed herein. An Adaptive Intelligence Engine (AIE) compiler is one example of a multi-core graph compiler. An compiler is used to mitigate performance degradation due to memory stalls (collisions) when executing an AIE compiler-accelerated application on an AI Engine. The method disclosed here addresses phase order issues to mitigate the memory collisions.