公开(公告)号：US10530379B1

公开(公告)日：2020-01-07

申请号：US16283692

申请日：2019-02-22

Applicant: Xilinx, Inc.

Inventor： Bruno Miguel Vaz ,  Brendan Farley

IPC: H03M1/06 ,  H03M1/10 ,  H03M1/12 ,  H03M1/46 ,  H03M1/00

Abstract: An analog-to-digital converter (ADC) circuit (400) and method of operation are disclosed. In some aspects, the ADC circuit (400) may include a plurality of channels (500), a gain calibration circuit (420), and a time-skew calibration circuit (430). Each of the plurality of channels (500) may include an ADC (520), a switch (510) configured to provide a differential input signal to the ADC (520), a calibration device (530), a multiplier (540), and a pseudorandom bit sequence (PRBS) circuit (550) to provide a pseudorandom number (PN) to the switch (510), to the calibration device (530), and to the multiplier (540). In some embodiments, the calibration device (530) may include first and second offset calibration circuits (531-532) coupled in parallel between a de-multiplexer (D1) and a multiplexer (M1) that alternately route signals to the first and second offset calibration circuits (531-532) based on the pseudorandom number (PN).

公开(公告)号：US11489503B1

公开(公告)日：2022-11-01

申请号：US17064595

申请日：2020-10-06

Applicant: XILINX, INC.

Inventor： Vipul Bajaj ,  Bruno Miguel Vaz

IPC: H03F3/45

Abstract: Cross-coupling of switched-capacitor output common-mode feedback capacitors in dynamic residue amplifiers is provided via a cross-coupled amplifier, comprising: a current source connected to a first node; a feedback capacitor connected to the first node and a second node; a feedback resistor connected between the second node and ground; an amplifier having an input connected to the second node; a gain transistor having: a drain connected to the first node; a source connected to ground; and a gate connected to an output of the amplifier; and a load capacitor connected to the first node and ground.

公开(公告)号：US11196412B1

公开(公告)日：2021-12-07

申请号：US16732851

申请日：2020-01-02

Applicant: Xilinx, Inc.

Inventor： Roswald Francis ,  Bruno Miguel Vaz

IPC: H03K17/687 ,  H03K17/12 ,  H03M1/12

Abstract: Apparatus and associated methods relate to an input buffer having a source follower connected in series with a push-pull driver to generate a shield reference node that provides conductive traces extending from the shield reference node and disposed between gate traces of the input buffer and a corresponding nearest reference potential node. In an illustrative example, the push-pull driver and the source follower may be capacitively coupled, via the gate traces, to receive an input signal from an input node. In some examples, the shield reference node may also include conductive traces disposed between the input node and/or the gate traces and a corresponding nearest reference potential node such that parts of parasitic capacitances in the input buffer may be shielded. Accordingly, the bandwidth of the input buffer may be advantageously improved. The high frequency return loss (S11) may also be improved accordingly.

公开(公告)号：US10826517B1

公开(公告)日：2020-11-03

申请号：US16680356

申请日：2019-11-11

Applicant: Xilinx, Inc.

Inventor： Bruno Miguel Vaz ,  John E. McGrath ,  Conrado K. Mesadri ,  Woon C. Wong ,  Ali Boumaalif ,  Christopher Erdman ,  Brendan Farley

IPC: H03M1/12 ,  H03M1/10 ,  G01R31/3185 ,  H04L12/43 ,  H04L12/433

Abstract: An integrated circuit is described. The integrated circuit comprises an analog-to-digital converter circuit configured to receive an input signal at an input and generate an output signal at an output; and a monitor circuit coupled to the output of the analog-to-digital converter circuit, the monitor circuit configured to receive the output signal and to generate integration coefficients for the analog-to-digital converter circuit; wherein the integration coefficients are dynamically generated based upon signal characteristics of the output signal generated by the analog-to-digital converter circuit. A method of receiving data in an integrated circuit is also described.

公开(公告)号：US10483996B1

公开(公告)日：2019-11-19

申请号：US15991539

申请日：2018-05-29

Applicant: Xilinx, Inc.

Inventor： Christophe Erdmann ,  Bob W. Verbruggen ,  Ali Boumaalif ,  Bruno Miguel Vaz

IPC: H03M1/12 ,  G06F1/10 ,  H03M1/66 ,  H03M1/06

Abstract: Apparatus and associated methods relate to modulating polarity on sample outputs from a time-interleaved analog-to-digital converter (TIADC) as an input to a time skew extractor in a clock skew calibration control loop. In an illustrative example, a multiplier-mixer may impart a polarity change to every other data sample transmitted between the TIADC and the time skew extractor. In some examples, a multiplexer may select between the polarity modulated samples and non-polarity modulated samples before the multiplier-mixer. Selection between the polarity modulated samples and the non-polarity modulated samples may be based on, for example, determination of specific frequency bands of an analog input signal. Various embodiments may improve convergence of clock skew calibration control loops for analog input signals sampled with a TIADC near a Nyquist frequency.

公开(公告)号：US10298248B1

公开(公告)日：2019-05-21

申请号：US15912318

申请日：2018-03-05

Applicant: Xilinx, Inc.

Inventor： Bruno Miguel Vaz ,  Christophe Erdmann ,  Bob W. Verbruggen ,  John E. McGrath ,  Ali Boumaalif

IPC: H03M1/10 ,  H03M1/12 ,  H03K19/177

Abstract: An example apparatus for analog-to-digital conversion includes a plurality of channels each including an analog-to-digital converter (ADC), a switch configured to couple a differential input to the ADC, a first offset calibration circuit coupled to an output of the ADC, a multiplier coupled to an output of the first offset calibration circuit, a second offset calibration circuit coupled to an output of the multiplier, and a pseudorandom bit sequence (PRBS) generator coupled to the switch and the multiplier. The apparatus further includes a gain calibration circuit coupled to an output of the second offset calibration circuit in each of the plurality of channels; and a time-skew calibration circuit coupled to an output of the gain calibration circuit.

公开(公告)号：US10291247B1

公开(公告)日：2019-05-14

申请号：US15914364

申请日：2018-03-07

Applicant: Xilinx, Inc.

Inventor： Bob W. Verbruggen ,  Christophe Erdmann ,  Bruno Miguel Vaz

IPC: H03M1/06 ,  H03M1/10 ,  H03M1/12

Abstract: An example time-skew calibration circuit includes a plurality of first circuits, each including a first accumulator and a second accumulator. The time-skew calibration circuit further includes a plurality of second circuits, each including a first adder coupled to outputs of the first accumulator and the second accumulator, and a first subtractor coupled to the outputs of the first accumulator and the second accumulator. The time-skew calibration circuit further includes a decision circuit configured to combine an output of the first adder and an output of the first subtractor.

公开(公告)号：US10218376B1

公开(公告)日：2019-02-26

申请号：US15807482

申请日：2017-11-08

Applicant: Xilinx, Inc.

Inventor： Diarmuid Collins ,  Bruno Miguel Vaz

IPC: H03M1/46 ,  H03M1/66

Abstract: An example capacitive digital-to-analog converter (CDAC) includes: a first plurality of capacitors consisting of M−1 capacitors, where M is an integer greater than one, the first plurality of capacitors including top plates coupled to a first node; a second plurality of capacitors consisting of M−1 capacitors, the second plurality of capacitors including top plates coupled to a second node; a first plurality of switches consisting of M−1 switches coupled to bottom plates of the respective M−1 capacitors of the first plurality of capacitors, the first plurality of switches further coupled to a third node providing a supply voltage and a fourth node providing a ground voltage; a second plurality of switches consisting of M−1 switches coupled to bottom plates of the respective M−1 capacitors of the second plurality of capacitors, the second plurality of switches coupled to the third node and the fourth node; and a control circuit including an input consisting of M bits for receiving an M bit code and an output consisting of 2*(M−1) bits for providing a first M−1 bit code to respectively control the M−1 switches of the first plurality of switches and a second M−1 bit code to respectively control the M−1 switches of the second plurality of switches.