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公开(公告)号：US10088726B2
公开(公告)日：2018-10-02
申请号：US15208928
申请日：2016-07-13
Inventor： Yao Yan , Shangcao Cao
IPC: G02F1/136 , G02F1/1368 , H01L27/12
Abstract: The array substrate, the liquid crystal display panel and the liquid crystal display device of the present disclosure are designed to from the MIS storage capacitor by the P—Si semiconductor layer, the first metal layer and the insulating layer between above or the P—Si semiconductor layer, the second metal layer and the dielectric spacer layer between above, when one side of the first metal layer or the second metal layer receiving the negative gray voltage, the P—Si in the P—Si semiconductor layer will gather to form the hole, when receiving the positive gray voltage, will form the depletion layer on the upper layer of the P—Si to reduce the capacity of the MIS storage capacitor, thereby reducing the difference of the capacitance when the MIS storage capacitor in the positive and negative gray voltage, improving the flicker phenomena and ensuring the display effect.
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公开(公告)号：US09959830B2
公开(公告)日：2018-05-01
申请号：US15026256
申请日：2016-02-24
Inventor： Juncheng Xiao , Yao Yan , Ronglei Dai , Shangcao Cao
IPC: G09G3/36
CPC classification number: G09G3/3677 , G09G3/36 , G09G3/3648 , G09G2300/0408 , G09G2310/0289 , G09G2310/08 , G09G2330/023 , G09G2340/145
Abstract: The present invention provides a GOA circuit, comprising a forward-backward scan control module, an output module, an output pull-down module, a node control module, a second node signal input module, a second node signal control module, a voltage stabilizing module and a second capacitor; the forward scan of the circuit is controlled with the ninth and the tenth thin film transistors, and the signal input of the second node is controlled with the first and the eleventh thin film transistors, and the mutual control of the first node and the second node are achieved with the second, the fourth and the fifth thin film transistors, and meanwhile, as the GOA circuit applies to a display of dual side drive interlaced scan structure, the GOA circuits of the two sides can respectively receive four different clock signals to reduce the loading of the signal line of the GOA circuit.
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公开(公告)号：US09922611B2
公开(公告)日：2018-03-20
申请号：US14915892
申请日：2016-01-28
IPC: G09G3/36 , H01L27/12 , G02F1/1333 , H01L29/786 , G02F1/1362 , G11C19/18
CPC classification number: G09G3/3674 , G02F1/13 , G02F1/1333 , G02F1/1362 , G09G3/36 , G09G2310/0286 , G11C19/184 , G11C19/28 , H01L27/1222 , H01L27/1237 , H01L29/78651
Abstract: The invention provides a GOA circuit for narrow border LCD panel, by disposing a first node leakage prevention unit (700) comprised of ninth TFT (T9), tenth TFT (T10) and third capacitor (C3), wherein the ninth TFT (T9) has gate and source connected to the output clock signal (CK) to form a diode structure to charge the third capacitor (C3) and fourth node (H(n)) to high voltage; the tenth TFT (T10) clears the fourth node during stage-propagated signal duration to ensure normal charging for the first node (Q(n)). The GOA circuit is applicable to dual-side progressive scanning architecture and also to dual-side interlaced scanning architecture, and able to prevent current leakage in the first node under dual-side interlaced scanning architecture to ensure stable operation of circuit and improve reliability of GOA circuit. Moreover, with only two clock signals on each side, the invention is suitable for narrow border display panel.
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公开(公告)号：US20180068628A1
公开(公告)日：2018-03-08
申请号：US15026256
申请日：2016-02-24
Inventor： Juncheng Xiao , Yao Yan , Ronglei Dai , Shangcao Cao
IPC: G09G3/36
CPC classification number: G09G3/3677 , G09G3/36 , G09G3/3648 , G09G2300/0408 , G09G2310/0289 , G09G2310/08 , G09G2330/023 , G09G2340/145
Abstract: The present invention provides a GOA circuit, comprising a forward-backward scan control module, an output module, an output pull-down module, a node control module, a second node signal input module, a second node signal control module, a voltage stabilizing module and a second capacitor; the forward scan of the circuit is controlled with the ninth and the tenth thin film transistors, and the signal input of the second node is controlled with the first and the eleventh thin film transistors, and the mutual control of the first node and the second node are achieved with the second, the fourth and the fifth thin film transistors, and meanwhile, as the GOA circuit applies to a display of dual side drive interlaced scan structure, the GOA circuits of the two sides can respectively receive four different clock signals to reduce the loading of the signal line of the GOA circuit.
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公开(公告)号：US09905182B2
公开(公告)日：2018-02-27
申请号：US14915222
申请日：2016-01-05
Inventor： Juncheng Xiao , Shangcao Cao , Ronglei Dai , Yao Yan
CPC classification number: G09G3/3677 , G06F3/0416 , G09G2300/0408 , G09G2310/0251 , G09G2310/0283 , G09G2310/0286 , G09G2310/08
Abstract: A GOA driving circuit, a TFT display panel and a display device are disclosed. The GOA driving circuit includes: an input module configured for outputting first control signals in accordance with the received display scanning signals and the touch scanning signals; an output module configured for outputting the first output control signals in accordance with the first control signals and the first clock signals; a pull-down module configured for outputting pull-down signals in accordance with the first control signals, the second control signals and the low level signals; and a pull-down maintaining module configure for outputting the second output control signals in accordance with the pull-down signals, the high level signals, and the first clock signals. The DC source is adopted to charge/discharge Qn to keep Qn at a reasonable level, and the transfer capability is enhanced. In addition, the forward scanning and the backward scanning may be implemented.
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Patent Agency Ranking
公开(公告)号：US20170102805A1
公开(公告)日：2017-04-13
申请号：US15009803
申请日：2016-01-28
Inventor： Juncheng Xiao , Shangcao Cao , Yao Yan , Ronglei Dai
IPC: G06F3/041
CPC classification number: G06F3/0412 , G06F3/044 , G06F2203/04103
Abstract: The invention discloses a GOA circuit for in-cell type touch display panel; during black screen, using a first global control signal to make a thirteenth N-type TFT conductive to raise a scan driving signal of each stage to high, using the first global control signal to make a twelfth N-type TFT conductive to pull down a voltage level of a second node, and pulling down a voltage level of a first node to avoid ineffective all-gate-on function; using a reset signal and a fourteenth N-type TFT to reset the second node to realize the normal output after awaking from black screen; during stop, setting a negative voltage as a pulse signal having same amplitude, phase and frequency as a touch signal, using a second global control signal to make the fifteenth N-type TFT conductive to output the negative voltage in pulse form to reduce cross-talk between the touch signal and a scan output end.
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公开(公告)号：US10324348B2
公开(公告)日：2019-06-18
申请号：US16127767
申请日：2018-09-11
Inventor： Yao Yan , Shangcao Cao
IPC: G02F1/136 , G02F1/1368 , H01L27/12 , G02F1/1362 , G02F1/1343
Abstract: The array substrate, the liquid crystal display panel and the liquid crystal display device of the present disclosure are designed to form the MIS storage capacitor by the P—Si semiconductor layer, the first metal layer and the insulating layer between above or the P—Si semiconductor layer, the second metal layer and the dielectric spacer layer between above, when one side of the first metal layer or the second metal layer receiving the negative gray voltage, the P—Si in the P—Si semiconductor layer will gather to form the hole, when receiving the positive gray voltage, will form the depletion layer on the upper layer of the P—Si to reduce the capacity of the MIS storage capacitor, thereby reducing the difference of the capacitance when the MIS storage capacitor in the positive and negative gray voltage, improving the flicker phenomena and ensuring the display effect.
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公开(公告)号：US10288967B2
公开(公告)日：2019-05-14
申请号：US16127704
申请日：2018-09-11
Inventor： Yao Yan , Shangcao Cao
IPC: G02F1/136 , G02F1/1368 , H01L27/12
Abstract: The array substrate, the liquid crystal display panel and the liquid crystal display device of the present disclosure are designed to form the MIS storage capacitor by the P—Si semiconductor layer, the first metal layer and the insulating layer between above or the P—Si semiconductor layer, the second metal layer and the dielectric spacer layer between above, when one side of the first metal layer or the second metal layer receiving the negative gray voltage, the P—Si in the P—Si semiconductor layer will gather to form the hole, when receiving the positive gray voltage, will form the depletion layer on the upper layer of the P—Si to reduce the capacity of the MIS storage capacitor, thereby reducing the difference of the capacitance when the MIS storage capacitor in the positive and negative gray voltage, improving the flicker phenomena and ensuring the display effect.
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公开(公告)号：US10268095B2
公开(公告)日：2019-04-23
申请号：US16126078
申请日：2018-09-10
Inventor： Yao Yan , Shangcao Cao
IPC: G02F1/136 , G02F1/1368 , H01L27/12
Abstract: The array substrate, the liquid crystal display panel and the liquid crystal display device of the present disclosure are designed to from the MIS storage capacitor by the P-Si semiconductor layer, the first metal layer and the insulating layer between above or the P-Si semiconductor layer, the second metal layer and the dielectric spacer layer between above, when one side of the first metal layer or the second metal layer receiving the negative gray voltage, the P-Si in the P-Si semiconductor layer will gather to form the hole, when receiving the positive gray voltage, will form the depletion layer on the upper layer of the P-Si to reduce the capacity of the MIS storage capacitor, thereby reducing the difference of the capacitance when the MIS storage capacitor in the positive and negative gray voltage, improving the flicker phenomena and ensuring the display effect.
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公开(公告)号：US10013942B2
公开(公告)日：2018-07-03
申请号：US14900684
申请日：2015-10-21
Applicant: Shenzhen China Star Optoelectronics Technology Co., Ltd. , Wuhan China Star Optoelectronics Technology Co., Ltd.
Inventor： Juncheng Xiao , Ronglei Dai , Shangcao Cao , Yao Yan
IPC: G09G3/36 , G02F1/1368 , G02F1/1362
CPC classification number: G09G3/3677 , G02F1/136286 , G02F1/1368 , G02F2203/64 , G09G2300/0408 , G09G2310/0245 , G09G2310/0286 , G09G2310/08 , G09G2320/0214 , G09G2330/026 , G11C19/28
Abstract: The disclosure provides a GOA circuit, a driving method thereof and a liquid crystal display device. The GOA circuit comprises a plurality of GOA units connected in cascade, wherein the N-stage GOA unit comprises a N-stage stage circuit, a N-stage Q point control circuit, a N-stage P point circuit, a N-stage output circuit and a switch circuit. The switch circuit is connected to the N-stage scan line for sending a turn-on signal to the N-stage scan line before the liquid crystal display device displays an image such that the thin-film transistor in the pixel connected to the N-stage scan line turns on. The disclosure may turn on the gate of each pixel when the display device is waken from the black screen to prevent the electricity leakage when the display device is wakened from the black screen, and may also increase the stability of the circuit.
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