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11.发明授权公开(公告)号：US10403219B2
公开(公告)日：2019-09-03
申请号：US15312040
申请日：2016-06-13
Inventor： Yafeng Li
IPC: G09G3/36 , G02F1/1368 , G02F1/1345 , H01L27/12 , G02F1/1362 , H01L29/786
Abstract: The present disclosure proposes a GOA circuit having GOA units connected in a serial. Each GOA unit includes a scan-control module, an output module, a pull-down module, and an output adjusting module. By using the output adjusting module formed by a ninth TFT, a tenth TFT, an eleventh TFT, and a twelfth TFT, the voltage level of a fourth node transits between the high voltage level and the low voltage level with the second clock signal in either forward scanning or backward scanning. Compared with the conventional technology where the high and low voltage levels of the output terminal are mainly realized using the second TFT, the GOA circuit realizes that the output ability of the output terminal enhances and the charging capacity of in-plane pixels upgrades in the same period of time to improve the display effect of the liquid crystal panel.
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公开(公告)号：US10156756B2
公开(公告)日：2018-12-18
申请号：US14907865
申请日：2016-01-12
Inventor： Yafeng Li , Xiangyi Peng
IPC: G02F1/1343
Abstract: A liquid crystal panel and a pixel structure thereof are described. The pixel structure has a common electrode, a protecting layer, a plurality of pixel electrodes, and a plurality of first channels. The protecting layer is located on the common electrode; the pixel electrodes are located on the protecting layer; and the first channels are located between the neighboring pixel electrodes and pass through the protecting layer, so that the first channels expose a top surface of the common electrode.
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公开(公告)号：US10146080B1
公开(公告)日：2018-12-04
申请号：US15738031
申请日：2017-11-30
Inventor： Yafeng Li , Jinfang Wu
IPC: G02F1/1335 , G02F1/1343
Abstract: The present invention provides a method for manufacturing a display device includes providing an array substrate with a plurality of pixel unit areas formed on a surface thereof; defining a dividing line; dividing the pixel unit areas to a pixel calculating area, a predetermined displaying area, and a predetermined shielding area, and dividing the pixel calculating area to a first part and a second part by the dividing line; calculating areas of sub pixels according to light extraction efficiencies and effective light extraction areas of the sub pixels; forming a shielding layer according to the areas of the sub pixels.
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14.发明授权公开(公告)号：US10126621B2
公开(公告)日：2018-11-13
申请号：US15126418
申请日：2016-06-30
Inventor： Yafeng Li
IPC: G02F1/1368 , G09G3/36
Abstract: The present disclosure proposes a GOA circuit based on LTPS TFTs. A ninth TFT is introduced to adjust the high and low voltage levels imposed on the second node P(n). The ninth TFT includes a gate and a source both electrically connected to the second node P(n) and a drain electrically connected to a second clock signal. Such designs make it possible that the level of the second node P(n) is pulled down according to a certain frequency when an output terminal G(n) keeps the low voltage level. So the second node P(n) does not need to keep the high voltage level all the time in the present invention. Also, the fourth and the seventh transistors T4 and T7 do not have the problem of a threshold voltage shift due to a long working time.
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公开(公告)号：US10078993B2
公开(公告)日：2018-09-18
申请号：US14905024
申请日：2015-12-23
Inventor： Yafeng Li
CPC classification number: G09G3/3677 , G09G2300/0426 , G09G2300/0809 , G09G2310/0286 , G11C19/184 , G11C19/28
Abstract: A GOA substrate includes N shift register units. The first stage shift register unit outputs a scan signal pulse based on a first clock signal and a start signal. The last stage shift register unit outputs a scan signal pulse based on Mth clock signal and the start signal. The start signal has a pulse width starting from a falling edge of the Mth clock signal of the last stage shift register unit when scanning a first frame, and ending at a rising edge of the first clock signal of the first stage shift register unit when scanning a second frame. Since the first and last shift register units are used to drive a scan signal pulse based on the start signal, the present invention reduces the number of wires needed to transmit start signals and simplifies the complexity of the layout design.
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Patent Agency Ranking
公开(公告)号：US20180218695A1
公开(公告)日：2018-08-02
申请号：US15506240
申请日：2016-12-30
Inventor： Yafeng Li
IPC: G09G3/36
CPC classification number: G09G3/3648 , G09G3/3677 , G09G2300/0426 , G09G2310/0286 , G09G2310/067 , G09G2310/08 , G11C19/18 , G11C19/28
Abstract: The present invention relates to a GOA circuit. The GOA circuit comprises: a first thin film transistor (T1) to a fourteenth thin film transistor (T14), a first capacitor (C1) and a second capacitor (C2). The present invention adds a control unit consisted of thin film transistors (T9-T14) on the basis of the GOA circuit structure according to prior art, and a set of control signals (Select1, Select2) of which phases are opposite is introduced. The main function is to divide the gate output of the GOA circuit into two. In some special display mode, the frequency corresponded with Data signal will be halved, and the corresponding drive power consumption will be decreased. The present invention provides a GOA circuit, which can effectively reduce the layout space occupied by the GOA circuit for having a certain help to the development of the narrow frame technology.
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公开(公告)号：US20180031623A1
公开(公告)日：2018-02-01
申请号：US14912924
申请日：2016-01-29
Inventor： Yafeng Li , Xiangyi Peng
IPC: G01R31/00 , G02F1/1368 , G01R31/08 , G02F1/1362
CPC classification number: G01R31/001 , G01R31/08 , G02F1/133345 , G02F1/136204 , G02F1/136286 , G02F1/1368 , G02F2001/136254 , G02F2001/136295 , G02F2202/104 , G09G3/006 , G09G3/3648 , G09G2300/0417
Abstract: The invention provides an ESD detection method for array substrate. By connecting the first metal layer on array substrate through the first wire to the first test point, connecting the second metal layer on array substrate through the second wire to the second test point, when ESD occurs on array substrate, the resistance detection device is used to measure the resistance between the first and second test points. If the resistance is positive infinity, ESD did not occur between the first and second metal layers; if the resistance is within a measurable range, ESD occurs between the first and second metal layers. The resistance is used to locate the location of ESD occurrence on array substrate. Compared to known method using microscope to search ESD location, the invention can locate ESD location on array substrate more accurately and rapidly to save time and labor as well as detection cost.
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公开(公告)号：US09805675B2
公开(公告)日：2017-10-31
申请号：US15012787
申请日：2016-02-01
IPC: G06F1/00 , G09G3/36 , H03K17/687
CPC classification number: G09G3/3648 , G09G3/3677 , G09G2300/0408 , G09G2310/08 , H03K17/6871
Abstract: The disclosure discloses a GOA circuit based on the LTPS, including a modulation circuit; a charging circuit; an input signal terminal and an output signal terminal. The modulation circuit and the charging circuit are connected to the input signal terminal and the output signal terminal to make the modulation circuit and the charging circuit in parallel connection, and the charging circuit is used to charge the output scanning signal during the mutation process to increase the mutation speed of the output scanning signal. Wherein the charging circuit is a switch including a control terminal, a first terminal, and a second terminal; the input signal terminal is connected to the first terminal of the charging circuit. The output signal terminal is connected to the second terminal and the control terminal of the charging circuit separately. A display apparatus including the GOA circuit based on the LTPS is also provided.
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公开(公告)号：US20210124206A1
公开(公告)日：2021-04-29
申请号：US16308483
申请日：2018-09-27
Inventor： Yafeng Li , Jinfang Wu
IPC: G02F1/1362 , G02F1/1333 , G02F1/1343 , G06F3/041
Abstract: The invention provides a TFT array substrate and LCD panel. the TFT array substrate comprises a first metal layer, a first interlayer insulating layer, a second metal layer, a second interlayer insulating layer and a third metal layer sequentially disposed above the substrate. The first, second and third metal layers comprise a plurality of first, second and third fanout lines in the fanout line area, respectively; two of the first, second, and third fanout lines are connected to the data lines, and the other is connected with the touch line; because the first interlayer insulating layer is disposed between the first and second fanout lines, and the second interlayer insulating layer is disposed between the third and second fanout lines, the first, second and third fanout lines can overlap, which can effectively reduce the fanout line area and help to achieve a narrow border.
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公开(公告)号：US10803809B2
公开(公告)日：2020-10-13
申请号：US15327304
申请日：2016-12-29
Inventor： Yafeng Li
IPC: G09G3/3266 , G09G3/36 , G09G3/20
Abstract: Disclosed are a gate driving circuit, a driving method thereof, and a display device which comprises the gate driving circuit. In the gate driving circuit, the Qn node in the nth stage circuit is precharged when an output signal of a Qn−1 node in a previous stage driving circuit and an output signal of a Qn+1 node in a next stage driving circuit are both in a high-level state. Both the Qn−1 node and the Qn+1 node are at low levels when the gate driving circuit is in an All Gate On display state, and thus a possibility of current leakage from the Qn node can be substantially reduced.
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