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公开(公告)号：US20220399383A1
公开(公告)日：2022-12-15
申请号：US17260982
申请日：2020-11-24
Inventor： Fei Ai , Jiyue Song , Dewei Song
IPC: H01L27/146 , G02F1/1362 , G02F1/1343
Abstract: An array substrate, a display panel, and an electronic device are provided. The array substrate includes a substrate, a first conductive layer including a first connection part, a fourth insulating layer disposed on the first conductive layer and provided with a second via, and a second conductive layer disposed on the fourth insulating layer and in the second via. The second conductive layer includes a second electrode, and the second electrode is connected to the first connection part through the second via.
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公开(公告)号：US11315958B2
公开(公告)日：2022-04-26
申请号：US16605417
申请日：2019-09-18
Inventor： Fei Ai , Dewei Song , Guoheng Yin
IPC: H01L27/12 , H01L29/786 , H01L29/66 , G02F1/1368
Abstract: An array substrate and a method of manufacturing the same are provided. The array substrate includes a substrate, a plurality of thin film transistors disposed on the substrate, and a planarization layer covering the plurality of thin film transistors and filled a region defined by the plurality of thin film transistors and the substrate.
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公开(公告)号：US11307468B2
公开(公告)日：2022-04-19
申请号：US16754332
申请日：2019-11-11
Inventor： Yuan Yan , Yong Xu , Dewei Song , Fei Ai
IPC: G02F1/1362 , H01L27/12 , G02F1/1333 , G06F3/041 , G02F1/1343
Abstract: The present disclosure provides an array substrate and a manufacturing method of the array substrate. The method includes sequentially forming an active layer and an insulating layer on a substrate; forming a common electrode layer and a first metal layer on the insulating layer using a same photomask, wherein the common electrode layer includes touch electrodes; and forming a second metal layer on the pixel electrode layer, wherein the second metal layer includes touch signal lines, and the touch signal lines electrically are electrically connected to the touch electrodes.
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公开(公告)号：US20220004066A1
公开(公告)日：2022-01-06
申请号：US16754332
申请日：2019-11-11
Inventor： Yuan Yan , Yong Xu , Dewei Song , Fei Ai
IPC: G02F1/1362 , H01L27/12 , G02F1/1343 , G02F1/1333 , G06F3/041
Abstract: The present disclosure provides an array substrate and a manufacturing method of the array substrate. The method includes sequentially forming an active layer and an insulating layer on a substrate; forming a common electrode layer and a first metal layer on the insulating layer using a same photomask, wherein the common electrode layer includes touch electrodes; and forming a second metal layer on the pixel electrode layer, wherein the second metal layer includes touch signal lines, and the touch signal lines electrically are electrically connected to the touch electrodes.
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公开(公告)号：US12075638B2
公开(公告)日：2024-08-27
申请号：US17278694
申请日：2021-02-26
Inventor： Jiyue Song , Fei Ai , Dewei Song , Fan Gong
CPC classification number: H10K30/80 , H10K39/32 , G06V40/1318
Abstract: An array substrate, a display panel, and a display device are provided by the present application. The array substrate includes a base substrate; a light-sensitive component layer disposed on the base substrate, wherein a plurality of light-sensitive components are disposed at intervals in the light-sensitive component layer; and a first light-shielding layer disposed on the light-sensitive component layer. An orthographic projection of the first light-shielding layer on the base substrate partially overlaps with an orthographic projection of each of the light-sensitive components on the array substrate.
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Patent Agency Ranking
公开(公告)号：US20240204000A1
公开(公告)日：2024-06-20
申请号：US17905175
申请日：2022-08-17
Inventor： Fei Ai , Dewei Song , Shiyu Long
IPC: H01L27/12
CPC classification number: H01L27/1222
Abstract: An array substrate and a display panel are provided. The array substrate includes an active layer. The active layer includes a channel portion and a doped portion. The doped portion includes a first doped layer and a second doped layer. The channel portion includes a first channel portion and a second channel portion. The first channel portion is connected to the first doped layer. The second channel portion is connected to the second doped layer. A part of the second channel portion overlaps with a part of the first doped layer, thus, a step-laminated structure is formed, and an overall performance of the device is improved.
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公开(公告)号：US20240038900A1
公开(公告)日：2024-02-01
申请号：US18050753
申请日：2022-10-28
Inventor： Zhifu Li , Guanghui Liu , Fei Ai , Dewei Song , Chengzhi Luo
IPC: H01L29/786 , H01L29/66
CPC classification number: H01L29/78696 , H01L29/66757 , H01L29/78633 , H01L29/78675
Abstract: A thin-film transistor (TFT) having a vertical structure and an electronic device are provided. The TFT having the vertical structure includes an insulating substrate and an active layer disposed on the insulating substrate. The active layer includes a first conductive part, an active section, and a second conductive part which are stacked. An orthographic projection of the first conductive part on the insulating substrate partly overlaps an orthographic projection of the second conductive part on the insulating substrate. Therefore, contamination ions may be prevented from entering the active section from the insulating substrate during manufacturing processes of the TFT. Thus, reliability of performance of the TFT may be improved.
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公开(公告)号：US11886064B2
公开(公告)日：2024-01-30
申请号：US16963787
申请日：2020-06-23
Inventor： Dewei Song , Fei Ai
IPC: G02F1/133 , G02F1/1333 , G02F1/1368 , H01L27/12
CPC classification number: G02F1/133354 , G02F1/1368 , H01L27/1248
Abstract: The present application provides a display panel and a display device. The display panel includes an array substrate, a color filter substrate, and a colloid layer. The array substrate includes a thin film transistor layer and a passivation layer. The passivation layer includes at least one first connection element. The color filter substrate is disposed opposite to the array substrate. The colloid layer is arranged between the passivation layer and the color filter substrate, the colloid layer is connected to the first connection element, and the colloid layer and the first connection element couple the array substrate to the color filter substrate.
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公开(公告)号：US20210098582A1
公开(公告)日：2021-04-01
申请号：US16097838
申请日：2018-09-14
Inventor： Yuan Yan , Lisheng Li , Dewei Song
IPC: H01L29/417 , H01L29/66 , H01L29/786 , H01L27/12
Abstract: The present invention teaches a TFT substrate manufacturing method and a TFT substrate. The method configures contact region vias in the source/drain contact regions at two ends of the active layer, provides buffer layer troughs in the buffer layer beneath the contact region vias, and forms undercut structure between the buffer layer troughs and the active layer around the contact region vias, thereby separating the transparent conductive layer at the contact region vias, and extending the source/drain electrodes to contact the source/drain contact regions of the active layer from below through the buffer layer troughs. The present invention therefore prevents the occurrence of Schottky contact barrier resulted from the contact between poly-Si and ITO in the 7-mask process by letting the source/drain electrodes to directly contact and form ohmic contact with the source/drain contact regions of the active layer, thereby enhancing the electronic mobility of TFT devices.
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公开(公告)号：US10784290B1
公开(公告)日：2020-09-22
申请号：US16475684
申请日：2019-04-30
Inventor： Fei Al , Dewei Song
IPC: H01L27/12 , H01L21/768 , H01L29/66 , H01L29/786
Abstract: A method of manufacturing an array substrate and an array substrate are provided. The method of manufacturing the array substrate includes forming a first metal layer on a substrate, wherein the first metal layer includes a plurality of first metal lines and a plurality of intermittent second metal lines, forming an interlayer dielectric insulating layer on the substrate and the first metal layer, and forming an intermittent data line on the interlayer dielectric insulating layer and the first metal layer, wherein the intermittent data line contacts the two ends of each of the intermittent second metal lines through the via holes.
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