-
公开(公告)号：US11387408B2
公开(公告)日：2022-07-12
申请号：US17131767
申请日：2020-12-23
发明人： Hui-Lin Wang , Chen-Yi Weng , Chin-Yang Hsieh , Yi-Hui Lee , Ying-Cheng Liu , Yi-An Shih , Jing-Yin Jhang , I-Ming Tseng , Yu-Ping Wang , Chien-Ting Lin , Kun-Chen Ho , Yi-Syun Chou , Chang-Min Li , Yi-Wei Tseng , Yu-Tsung Lai , Jun Xie
摘要： A magnetoresistive random access memory (MRAM), including a bottom electrode layer on a substrate, a magnetic tunnel junction stack on the bottom electrode layer, and a top electrode layer on the magnetic tunnel junction stack, wherein the material of top electrode layer is titanium nitride, and the percentage of nitrogen in the titanium nitride gradually decreases from the top surface of top electrode layer to the bottom surface of top electrode layer.
-
12.发明授权公开(公告)号：US11309486B2
公开(公告)日：2022-04-19
申请号：US16719992
申请日：2019-12-19
发明人： Hung-Chan Lin , Yu-Ping Wang , Hung-Yueh Chen
摘要： A magnetoresistive random access memory (MRAM) is provided in the present invention, including a conductive plug with a protruding portion extending outwardly on one side and a notched portion concaving inwardly on the other side of the upper edge of conductive plug, and a memory cell with a bottom electrode electrically connecting with the conductive plug, a magnetic tunnel junction (MTJ) on the bottom electrode, and a top electrode on the magnetic tunnel junction, wherein the bottom surface of memory cell completely overlaps the top surface of conductive plug.
-
公开(公告)号：US20220102621A1
公开(公告)日：2022-03-31
申请号：US17086447
申请日：2020-11-01
发明人： Hui-Lin Wang , Chen-Yi Weng , Si-Han Tsai , Che-Wei Chang , Po-Kai Hsu , Jing-Yin Jhang , Yu-Ping Wang , Ju-Chun Fan , Ching-Hua Hsu , Yi-Yu Lin , Hung-Yueh Chen
摘要： A method for fabricating a semiconductor device includes the steps of forming a magnetic tunneling junction (MTJ) on a MRAM region of a substrate, forming a first inter-metal dielectric (IMD) layer around the MTJ, forming a patterned mask on a logic region of the substrate, performing a nitridation process to transform part of the first IMD layer to a nitride layer, forming a first metal interconnection on the logic region, forming a stop layer on the first IMD layer, forming a second IMD layer on the stop layer, and forming a second metal intercom in the second IMD layer to connect to the MTJ.
-
公开(公告)号：US20210343786A1
公开(公告)日：2021-11-04
申请号：US16882783
申请日：2020-05-26
发明人： Hui-Lin Wang , Po-Kai Hsu , Jing-Yin Jhang , Yu-Ping Wang , Hung-Yueh Chen , Wei Chen
摘要： A method for fabricating a semiconductor device includes the steps of: forming a magnetic tunneling junction (MTJ) on a substrate; forming a first inter-metal dielectric (IMD) layer around the MTJ; forming a first metal interconnection adjacent to the MTJ; forming a stop layer on the first IMD layer; removing the stop layer to form an opening; and forming a channel layer in the opening to electrically connect the MTJ and the first metal interconnection.
-
公开(公告)号：US20210296572A1
公开(公告)日：2021-09-23
申请号：US17341417
申请日：2021-06-08
发明人： Hui-Lin Wang , Chen-Yi Weng , Yi-Wei Tseng , Chin-Yang Hsieh , Jing-Yin Jhang , Yi-Hui Lee , Ying-Cheng Liu , Yi-An Shih , I-Ming Tseng , Yu-Ping Wang
摘要： A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a first spacer on one side of the of the MTJ, a second spacer on another side of the MTJ, a first metal interconnection on the MTJ, and a liner adjacent to the first spacer, the second spacer, and the first metal interconnection. Preferably, each of a top surface of the MTJ and a bottom surface of the first metal interconnection includes a planar surface and two sidewalls of the first metal interconnection are aligned with two sidewalls of the MTJ.
-
公开(公告)号：US11087812B1
公开(公告)日：2021-08-10
申请号：US16931438
申请日：2020-07-16
发明人： Yi-Hui Lee , I-Ming Tseng , Chiu-Jung Chiu , Chung-Liang Chu , Yu-Chun Chen , Ya-Sheng Feng , Yi-An Shih , Hsiu-Hao Hu , Yu-Ping Wang
摘要： A MRAM includes a plurality of memory cells, an operation unit, a voltage generator, and an input/output circuit. The operation unit includes multiple groups of memory cells among the plurality of memory cells. The voltage generator is configured to provide a plurality of control signals by voltage-dividing a voltage control signal and selectively output the plurality of control signals to the input/output circuit. The input/output circuit is configured to output a plurality of switching pulse signals to the multiple groups of memory cells according to the plurality of control signals, wherein each switching pulse signal differs in pulse width or level.
-
公开(公告)号：US20210167281A1
公开(公告)日：2021-06-03
申请号：US16732359
申请日：2020-01-02
发明人： Hui-Lin Wang , Po-Kai Hsu , Hung-Yueh Chen , Yu-Ping Wang
摘要： A method for fabricating semiconductor device includes the steps of: forming a magnetic tunneling junction (MTJ) stack on a substrate; forming a top electrode on the MTJ stack; performing a first patterning process to remove the MTJ stack for forming a first MTJ; forming a first inter-metal dielectric (IMD) layer around the first MTJ; and performing a second patterning process to remove the first MTJ for forming a second MTJ and a third MTJ.
-
公开(公告)号：US20210074907A1
公开(公告)日：2021-03-11
申请号：US16589157
申请日：2019-10-01
发明人： Hui-Lin Wang , Po-Kai Hsu , Chen-Yi Weng , Jing-Yin Jhang , Yu-Ping Wang , Hung-Yueh Chen
摘要： A method for fabricating semiconductor device includes the steps of: forming a substrate having a magnetic tunneling junction (MTJ) region and a logic region; forming a MTJ on the MTJ region; forming a top electrode on the MTJ; forming an inter-metal dielectric (IMD) layer around the MTJ; removing the IMD layer directly on the top electrode to form a recess; forming a first hard mask on the IMD layer and into the recess; removing the first hard mask and the IMD layer on the logic region to form a contact hole; and forming a metal layer in the recess and the contact hole to form a connecting structure on the top electrode and a metal interconnection on the logic region.
-
公开(公告)号：US20210036053A1
公开(公告)日：2021-02-04
申请号：US17074643
申请日：2020-10-20
发明人： Hui-Lin Wang , Chia-Chang Hsu , Chen-Yi Weng , Hung-Chan Lin , Jing-Yin Jhang , Yu-Ping Wang
IPC分类号： H01L27/22 , G11C11/16 , H01L23/48 , H01L43/12 , H01L23/544 , H01L21/321 , H01L21/762 , H01L23/485
摘要： The disclosure provides a semiconductor memory device including a substrate having a memory cell region and an alignment mark region; a dielectric layer covering the memory cell region and the alignment mark region; conductive vias in the dielectric layer within the memory cell region; an alignment mark trench in the dielectric layer within the alignment mark region; and storage structures disposed on the conductive vias, respectively. Each of the storage structures includes a bottom electrode defined from a bottom electrode metal layer, a magnetic tunnel junction (MTJ) structure defined from an MTJ layer, and a top electrode. A residual metal stack is left in the alignment mark trench. The residual metal stack includes a portion of the bottom electrode metal layer and a portion of the MTJ layer.
-
公开(公告)号：US20210020832A1
公开(公告)日：2021-01-21
申请号：US17064606
申请日：2020-10-07
发明人： Ching-Wen Hung , Yu-Ping Wang
摘要： A method for fabricating semiconductor device includes the steps of first providing a substrate having a magnetic tunnel junction (MTJ) region and an edge region, forming an first inter-metal dielectric (IMD) layer on the substrate, and then forming a first MTJ and a second MTJ on the first IMD layer, in which the first MTJ is disposed on the MTJ region while the second MTJ is disposed on the edge region. Next, a second IMD layer is formed on the first MTJ and the second MTJ.
-
-
-
-
-
-
-
-
-
搜索结果
162 条记录 (耗时 0.02 秒)
