公开(公告)号：US10707092B1

公开(公告)日：2020-07-07

申请号：US16245163

申请日：2019-01-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Hung Wang ,  En-Chiuan Liou ,  Chien-Hao Chen ,  Jhao-Hao Lee ,  Sho-Shen Lee ,  Chih-Yu Chiang

IPC: H01L21/00 ,  H01L21/311 ,  H01L21/768 ,  H01L21/033 ,  H01L27/108

Abstract: The present invention provides a method of fabricating a semiconductor pattern. Firstly, a substrate is provided, having an oxide layer thereon and a first material layer on the oxide layer, a first region and a second region are defined on the substrate. A first etching step is performed, to remove a portion of the first material layer in the first region, and then a plurality of first patterns are formed on the first material layer in the first region. A second composite layer is formed on the first pattern. Next, a second pattern layer is formed on the second composite layer in the first region, and a second etching step is performed, using the first pattern and the second pattern as a mask, to remove a portion of the second composite layer, a portion of the first material layer and a portion of the oxide layer.

公开(公告)号：US10079185B1

公开(公告)日：2018-09-18

申请号：US15630966

申请日：2017-06-23

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Chien-Hao Chen ,  Chien-Wei Huang ,  Chia-Hung Wang ,  Sho-Shen Lee

IPC: H01L21/66 ,  G01R31/26

Abstract: A semiconductor pattern for monitoring overlay and critical dimension at post-etching stage is provided in the present invention, which include a first inverted-T shaped pattern with a base portion and a middle portion extending from the base portion and a second pattern adjacent and spaced apart from the base portion of the first inverted-T shaped pattern, wherein the first inverted-T shaped pattern and the second pattern are composed of a plurality of spacer patterns spaced apart from each other.

公开(公告)号：US20190035743A1

公开(公告)日：2019-01-31

申请号：US16003090

申请日：2018-06-07

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Feng-Yi Chang ,  Fu-Che Lee ,  Yi-Wang Zhan ,  Chia-Liang Liao ,  Yu-Cheng Tung ,  Chien-Hao Chen ,  Chia-Hung Wang

IPC: H01L23/544 ,  H01L27/108

CPC classification number: H01L23/544 ,  H01L21/31116 ,  H01L21/31144 ,  H01L27/108 ,  H01L27/10808 ,  H01L27/10852 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/5446

Abstract: A semiconductor structure is disclosed. The semiconductor structure includes a substrate having a scribe line region. A material layer is formed on the scribe line region and has a rectangular region defined therein. The rectangular region has a pair of first edges parallel with a widthwise direction of the scribe line region and a pair of second edges parallel with a lengthwise direction of the scribe line region. A pair of first alignment features is formed in the material layer along the first edges, and a pair of second alignment features is formed in the material layer along the second edges. The space between the pair of first alignment features is larger than a space between the pair of the second alignment features.

公开(公告)号：US09753373B2

公开(公告)日：2017-09-05

申请号：US14940108

申请日：2015-11-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Chia-Hung Wang

IPC: G03B27/42 ,  G03F7/20 ,  G01B11/27

CPC classification number: G03F7/70141 ,  G01B11/272 ,  G03F7/70633

Abstract: A semiconductor processing method is provided and includes the following steps. A first semiconductor process is performed for a wafer to obtain plural overlay datum (x, y), wherein x and y are respectively shift values in X-direction and Y-direction. Next, A re-correct process is performed by a computer, wherein the re-correct process comprises: (a) providing an overlay tolerance value (A, B) and an original out of specification value (OOS %), wherein A and B are respectively predetermined tolerance values in X-direction and Y-direction; (b) providing at least a k value (kx, ky); (c) modifying the overlay datum (x, y) according to the k value (kx, ky) to obtain at least a revised overlay datum (x′, y′); and (d) calculating a process parameter from the revised overlay datum (x′, y′). Lastly, a second semiconductor process is performed according to the process parameter . . . . The present invention further provides a lithography system.

公开(公告)号：US09490217B1

公开(公告)日：2016-11-08

申请号：US14687912

申请日：2015-04-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Ching Lin ,  En-Chiuan Liou ,  Chia-Hung Wang ,  Sho-Shen Lee

IPC: H01L23/544 ,  H01L21/68 ,  H01L29/78

CPC classification number: H01L29/785 ,  G03F7/70633 ,  G03F7/70683

Abstract: An overlay mark for determining the alignment between two separately generated patterns formed along with two successive layers above a substrate is provided in the present invention, wherein both the substrate and the overlay mark include at least two pattern zones having periodic structures with different orientations, and the periodic structures of the overlay mark are orthogonally overlapped with the periodic structures of the substrate.

Abstract translation: 在本发明中提供了用于确定在衬底上方与两个连续层形成的两个单独产生的图案之间的对准的覆盖标记，其中衬底和覆盖标记都包括具有不同取向的周期性结构的至少两个图案区域，以及 覆盖标记的周期性结构与衬底的周期性结构正交地重叠。

公开(公告)号：US20150362905A1

公开(公告)日：2015-12-17

申请号：US14457136

申请日：2014-08-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Chia-Chang Hsu ,  Teng-Chin Kuo ,  Chia-Hung Wang ,  Tuan-Yen Yu ,  Yuan-Chi Pai ,  Chun-Chi Yu

IPC: G05B19/18 ,  G03F7/20

CPC classification number: G03F7/70633 ,  G03F1/42 ,  G03F7/70491 ,  G05B19/188 ,  G05B2219/45027 ,  G05B2219/45031

Abstract: A method of correcting an overlay error includes the following steps. First, an overlay mark disposed on a substrate is captured so as to generate overlay mark information. The overlay mark includes at least a pair of first mark patterns and at least a second mark pattern above the first mark patterns. Then, the overlay mark information is calculated to generate an offset value between two first mark patterns and to generate a shift value between the second mark pattern and one of the first mark patterns. Finally, the offset value is used to compensate the shift value so as to generate an amended shift value.

Abstract translation: 校正重叠错误的方法包括以下步骤。 首先，捕获设置在基板上的覆盖标记，以生成重叠标记信息。 覆盖标记包括至少一对第一标记图案和至少第一标记图案上方的第二标记图案。 然后，计算叠加标记信息以产生两个第一标记图案之间的偏移值，并产生第二标记图案与第一标记图案之一之间的偏移值。 最后，偏移值用于补偿偏移值，以产生修正的移位值。