公开(公告)号：US20140117532A1

公开(公告)日：2014-05-01

申请号：US13660441

申请日：2012-10-25

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chita Chuang ,  Yao-Chun Chuang ,  Yu-Chen Hsu ,  Ming Hung Tseng ,  Chen-Shien Chen

IPC: H01L23/485 ,  H01L21/60

CPC classification number: H01L24/13 ,  H01L24/05 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/05567 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/13022 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/81024 ,  H01L2224/81447 ,  H01L2224/81815 ,  H01L2224/81911 ,  H01L2924/00014 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/00 ,  H01L2924/01047 ,  H01L2924/0103 ,  H01L2924/01083 ,  H01L2924/01049 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01029 ,  H01L2924/01051 ,  H01L2224/05552

Abstract: The disclosure is directed to a device and method for manufacture thereof. The device includes a first workpiece bonded to a second workpiece by a bump interconnection structure. The bump interconnection structure allows for optimized packaging assembly yield and bond integrity.

Abstract translation: 本公开涉及一种用于制造其的装置及其方法。 该装置包括通过凸块互连结构接合到第二工件的第一工件。 凸块互连结构允许优化的包装组装产量和粘合完整性。

公开(公告)号：US12046566B2

公开(公告)日：2024-07-23

申请号：US17481003

申请日：2021-09-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Min-Feng Ku ,  Yao-Chun Chuang ,  Ching-Pin Lin ,  Cheng-Chien Li

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/00 ,  H01L23/58

CPC classification number: H01L23/585 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/564

Abstract: A semiconductor article which includes a semiconductor substrate, a back end of the line (BEOL) wiring portion on the semiconductor substrate, a through silicon via and a guard ring. The semiconductor substrate is made of a semiconductor material. The BEOL wiring portion includes a plurality of wiring layers having electrically conductive wiring and electrical insulating material. The through silicon via provides a conductive path through the BEOL wiring portion and the semiconductor substrate. The guard ring surrounds the through silicon via in the BEOL wiring portion and in some embodiments in the semiconductor substrate.

公开(公告)号：US20230369199A1

公开(公告)日：2023-11-16

申请号：US18359011

申请日：2023-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yuan-Yang Hsiao ,  Hsiang-Ku Shen ,  Dian-Hau Chen ,  Hsiao Ching-Wen ,  Yao-Chun Chuang

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/528

CPC classification number: H01L23/5223 ,  H01L21/76843 ,  H01L28/40 ,  H01L23/528 ,  H01L28/91 ,  H10B12/033

Abstract: A metal-insulator-metal (MIM) structure and methods of forming the same for reducing the accumulation of external stress at the corners of the conductor layers are disclosed herein. An exemplary device includes a substrate that includes an active semiconductor device. A stack of dielectric layers is disposed over the substrate. A lower contact is disposed over the stack of dielectric layers. A passivation layer is disposed over the lower contact. A MIM structure is disposed over the passivation layer, the MIM structure including a first conductor layer, a second conductor layer disposed over the first conductor layer, and a third conductor layer disposed over the second conductor layer. A first insulator layer is disposed between the first conductor layer and the second conductor layer. A second insulator layer is disposed between the second conductor layer and the third conductor layer. One or more corners of the third conductor layer are rounded.

公开(公告)号：US11728262B2

公开(公告)日：2023-08-15

申请号：US17470680

申请日：2021-09-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yuan-Yang Hsiao ,  Hsiang-Ku Shen ,  Dian-Hau Chen ,  Hsiao Ching-Wen ,  Yao-Chun Chuang

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/528 ,  H10B12/00 ,  H01L49/02

CPC classification number: H01L23/5223 ,  H01L21/76843 ,  H01L23/528 ,  H01L28/40 ,  H01L28/91 ,  H10B12/033

Abstract: A metal-insulator-metal (MIM) structure and methods of forming the same for reducing the accumulation of external stress at the corners of the conductor layers are disclosed herein. An exemplary device includes a substrate that includes an active semiconductor device. A stack of dielectric layers is disposed over the substrate. A lower contact is disposed over the stack of dielectric layers. A passivation layer is disposed over the lower contact. A MIM structure is disposed over the passivation layer, the MIM structure including a first conductor layer, a second conductor layer disposed over the first conductor layer, and a third conductor layer disposed over the second conductor layer. A first insulator layer is disposed between the first conductor layer and the second conductor layer. A second insulator layer is disposed between the second conductor layer and the third conductor layer. One or more corners of the third conductor layer are rounded.

公开(公告)号：US20200321326A1

公开(公告)日：2020-10-08

申请号：US16907597

申请日：2020-06-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yao-Chun Chuang ,  Yu-Chen Hsu ,  Hao Chun Liu ,  Chita Chuang ,  Chen-Cheng Kuo ,  Chen-Shien Chen

IPC: H01L25/00 ,  H01L21/56 ,  H01L23/31 ,  H01L23/00 ,  H01L25/065

Abstract: A method comprises depositing a protection layer over a first substrate, wherein the first substrate is part of a first semiconductor die, forming an under bump metallization structure over the protection layer, forming a connector over the under bump metallization structure, forming a first dummy plane along a first edge of a top surface of the first semiconductor die and forming a second dummy plane along a second edge of the top surface of the first semiconductor die, wherein the first dummy plane and the second dummy plane form an L-shaped region.