公开(公告)号：US11955338B2

公开(公告)日：2024-04-09

申请号：US18161662

申请日：2023-01-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Chun Huang ,  Ya-Wen Yeh ,  Chien-Wen Lai ,  Wei-Liang Lin ,  Ya Hui Chang ,  Yung-Sung Yen ,  Ru-Gun Liu ,  Chin-Hsiang Lin ,  Yu-Tien Shen

IPC: H01L21/033 ,  C23C16/04 ,  C23C16/458 ,  C23C16/50 ,  H01L21/02 ,  H01L21/266 ,  H01L21/308 ,  H01L21/3205

CPC classification number: H01L21/0337 ,  C23C16/042 ,  C23C16/4582 ,  C23C16/50 ,  H01L21/02274 ,  H01L21/266 ,  H01L21/3086 ,  H01L21/32051

Abstract: A method includes providing a substrate having a surface such that a first hard mask layer is formed over the surface and a second hard mask layer is formed over the first hard mask layer, forming a first pattern in the second hard mask layer, where the first pattern includes a first mandrel oriented lengthwise in a first direction and a second mandrel oriented lengthwise in a second direction different from the first direction, and where the first mandrel has a top surface, a first sidewall, and a second sidewall opposite to the first sidewall, and depositing a material towards the first mandrel and the second mandrel such that a layer of the material is formed on the top surface and the first sidewall but not the second sidewall of the first mandrel.

公开(公告)号：US11796922B2

公开(公告)日：2023-10-24

申请号：US16587710

申请日：2019-09-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Ru-Gun Liu ,  Huicheng Chang ,  Chia-Cheng Chen ,  Jyu-Horng Shieh ,  Liang-Yin Chen ,  Shu-Huei Suen ,  Wei-Liang Lin ,  Ya Hui Chang ,  Yi-Nien Su ,  Yung-Sung Yen ,  Chia-Fong Chang ,  Ya-Wen Yeh ,  Yu-Tien Shen

IPC: G03F1/22 ,  G03F7/36 ,  G03F7/00 ,  G03F7/40 ,  H01L21/027 ,  G03F1/36 ,  G03F1/70

CPC classification number: G03F7/70558 ,  G03F1/22 ,  G03F1/36 ,  G03F1/70 ,  G03F7/0035 ,  G03F7/40 ,  G03F7/70033 ,  G03F7/70625 ,  H01L21/0274

Abstract: In a method of forming a pattern, a photo resist layer is formed over an underlying layer, the photo resist layer is exposed to an actinic radiation carrying pattern information, the exposed photo resist layer is developed to form a developed resist pattern, a directional etching operation is applied to the developed resist pattern to form a trimmed resist pattern, and the underlying layer is patterned using the trimmed resist pattern as an etching mask.

公开(公告)号：US11791161B2

公开(公告)日：2023-10-17

申请号：US17114070

申请日：2020-12-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Tien Shen ,  Ya-Wen Yeh ,  Wei-Liang Lin ,  Ya Hui Chang ,  Yung-Sung Yen ,  Wei-Hao Wu ,  Li-Te Lin ,  Ru-Gun Liu ,  Kuei-Shun Chen

IPC: G03F7/09 ,  H01L21/027 ,  H01L21/033 ,  H01L21/311 ,  H01L21/306 ,  G03F7/20 ,  G03F7/11

CPC classification number: H01L21/0273 ,  G03F7/09 ,  H01L21/0337 ,  H01L21/311 ,  G03F7/11 ,  G03F7/20 ,  H01L21/0274 ,  H01L21/306

Abstract: The present disclosure provides a method for semiconductor manufacturing in accordance with some embodiments. The method includes providing a substrate and a patterning layer over the substrate and forming a plurality of openings in the patterning layer. The substrate includes a plurality of features to receive a treatment process. The openings partially overlap with the features from a top view while a portion of the features remains covered by the patterning layer. Each of the openings is free of concave corners. The method further includes performing an opening expanding process to enlarge each of the openings and performing a treatment process to the features through the openings. After the opening expanding process, the openings fully overlap with the features from the top view.

公开(公告)号：US20230170218A1

公开(公告)日：2023-06-01

申请号：US18161662

申请日：2023-01-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Chun Huang ,  Ya-Wen Yeh ,  Chien-Wen Lai ,  Wei-Liang Lin ,  Ya Hui Chang ,  Yung-Sung Yen ,  Ru-Gun Liu ,  Chin-Hsiang Lin ,  Yu-Tien Shen

IPC: H01L21/033 ,  H01L21/02 ,  C23C16/458 ,  C23C16/50 ,  C23C16/04 ,  H01L21/3205 ,  H01L21/308 ,  H01L21/266

CPC classification number: H01L21/0337 ,  C23C16/042 ,  C23C16/50 ,  C23C16/4582 ,  H01L21/266 ,  H01L21/02274 ,  H01L21/3086 ,  H01L21/32051

Abstract: A method includes providing a substrate having a surface such that a first hard mask layer is formed over the surface and a second hard mask layer is formed over the first hard mask layer, forming a first pattern in the second hard mask layer, where the first pattern includes a first mandrel oriented lengthwise in a first direction and a second mandrel oriented lengthwise in a second direction different from the first direction, and where the first mandrel has a top surface, a first sidewall, and a second sidewall opposite to the first sidewall, and depositing a material towards the first mandrel and the second mandrel such that a layer of the material is formed on the top surface and the first sidewall but not the second sidewall of the first mandrel.

公开(公告)号：US11289332B2

公开(公告)日：2022-03-29

申请号：US16512336

申请日：2019-07-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Shih-Chun Huang ,  Chin-Hsiang Lin ,  Chien-Wen Lai ,  Ru-Gun Liu ,  Wei-Liang Lin ,  Ya Hui Chang ,  Yung-Sung Yen ,  Yu-Tien Shen ,  Ya-Wen Yeh

IPC: H01L21/033 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/768 ,  H01L21/3105

Abstract: A method of fabricating a semiconductor device includes forming a hard mask layer over a substrate. A multi-layer resist is formed over the hard mask layer. The multi-layer resist is etched to form a plurality of openings in the multi-layer resist to expose a portion of the hard mask layer. Ion are directionally provided at an angle to the multi-layer resist to predominately contact sidewalls of the plurality of openings in the multi-layer resist rather than the hard mask layer. In one embodiment, the multi-layer resist is directionally etched by directing etch ions at an angle to predominately contact sidewalls of the plurality of openings in the multi-layer resist rather than the hard mask layer. In another embodiment, the multi-layer resist is directionally implanted by directing implant ions at an angle to predominately contact sidewalls of the plurality of openings in the multi-layer resist rather than the hard mask layer.

公开(公告)号：US20210358752A1

公开(公告)日：2021-11-18

申请号：US17384921

申请日：2021-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Chun Huang ,  Ya-Wen Yeh ,  Chien-Wen Lai ,  Wei-Liang Lin ,  Ya Hui Chang ,  Yung-Sung Yen ,  Ru-Gun Liu ,  Chin-Hsiang Lin ,  Yu-Tien Shen

IPC: H01L21/033 ,  H01L21/02 ,  C23C16/458 ,  C23C16/50 ,  C23C16/04 ,  H01L21/3205 ,  H01L21/308 ,  H01L21/266

Abstract: A method of depositing a material on one of two, but not both, sidewalls of a raised structure formed on a substrate includes tilting a normal of the substrate away from a source of the deposition material or tilting the source of the deposition material away from the normal of the substrate. The method may be implemented by a plasma-enhanced chemical vapor deposition (PECVD) technique.

公开(公告)号：US11094556B2

公开(公告)日：2021-08-17

申请号：US16383539

申请日：2019-04-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Ya-Wen Yeh ,  Yu-Tien Shen ,  Shih-Chun Huang ,  Po-Chin Chang ,  Wei-Liang Lin ,  Yung-Sung Yen ,  Wei-Hao Wu ,  Li-Te Lin ,  Pinyen Lin ,  Ru-Gun Liu

IPC: H01L21/3213 ,  H01L21/66

Abstract: In a method of manufacturing a semiconductor device, an underlying structure is formed over a substrate. A film is formed over the underlying structure. Surface topography of the film is measured and the surface topography is stored as topography data. A local etching is performed by using directional etching and scanning the substrate so that an entire surface of the film is subjected to the directional etching. A plasma beam intensity of the directional etching is adjusted according to the topography data.

公开(公告)号：US10861698B2

公开(公告)日：2020-12-08

申请号：US15689172

申请日：2017-08-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Tien Shen ,  Ya-Wen Yeh ,  Wei-Liang Lin ,  Ya Hui Chang ,  Yung-Sung Yen ,  Wei-Hao Wu ,  Li-Te Lin ,  Ru-Gun Liu ,  Kuei-Shun Chen

IPC: H01L21/027 ,  H01L21/033 ,  G03F7/09 ,  H01L21/311 ,  H01L21/306 ,  G03F7/20 ,  G03F7/11

Abstract: The present disclosure provides a method for semiconductor manufacturing in accordance with some embodiments. The method includes providing a substrate and a patterning layer over the substrate, wherein the substrate includes a plurality of features to receive a treatment process; forming at least one opening in the patterning layer, wherein the plurality of features is partially exposed in the at least one opening; applying a directional etching to expand the at least one opening in a first direction, thereby forming at least one expanded opening; and performing the treatment process to the plurality of features through the at least one expanded opening.

公开(公告)号：US20190157084A1

公开(公告)日：2019-05-23

申请号：US16107699

申请日：2018-08-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Chun Huang ,  Ya-Wen Yeh ,  Chien Wen Lai ,  Wei-Liang Lin ,  Ya Hui Chang ,  Yung-Sung Yen ,  Ru-Gun Liu ,  Chin-Hsiang Lin ,  Yu-Tien Shen

IPC: H01L21/033 ,  H01L21/02 ,  C23C16/04 ,  C23C16/50 ,  C23C16/458

Abstract: A method of depositing a material on one of two, but not both, sidewalls of a raised structure formed on a substrate includes tilting a normal of the substrate away from a source of the deposition material or tilting the source of the deposition material away from the normal of the substrate. The method may be implemented by a plasma-enhanced chemical vapor deposition (PECVD) technique.

公开(公告)号：US20190148147A1

公开(公告)日：2019-05-16

申请号：US16178417

申请日：2018-11-01

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Shih-Chun Huang ,  Chiu-Hsiang Chen ,  Ya-Wen Yeh ,  Yu-Tien Shen ,  Po-Chin Chang ,  Chien Wen Lai ,  Wei-Liang Lin ,  Ya Hui Chang ,  Yung-Sung Yen ,  Li-Te Lin ,  Pinyen Lin ,  Ru-Gun Liu ,  Chin-Hsiang Lin

IPC: H01L21/033 ,  H01L21/027 ,  H01L21/311 ,  H01L21/02 ,  H01L21/265

Abstract: A method of manufacturing a semiconductor device including operations of forming a first hard mask over an underlying layer on a substrate by a photolithographic and etching method, forming a sidewall spacer pattern having a first sidewall portion and a second sidewall portion on opposing sides of the first hard mask, etching the first sidewall portion, etching the first hard mask and leaving the second sidewall portion bridging a gap of the etched first hard mask, and processing the underlying layer using the second hard mask.