公开(公告)号：US09761546B2

公开(公告)日：2017-09-12

申请号：US15051197

申请日：2016-02-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Yu Cheng ,  Chih-Ping Chao ,  Kuan-Chi Tsai ,  Shih-Shiung Chen ,  Wei-Kung Tsai

IPC: H01L23/66 ,  H01L23/528 ,  H01L29/10 ,  H01L23/48 ,  H01L23/31 ,  H01L21/768 ,  H01L21/683 ,  H01L23/00 ,  H01L21/28 ,  H01L21/84 ,  H01L21/762 ,  H01L27/12

CPC classification number: H01L23/66 ,  H01L21/28008 ,  H01L21/6835 ,  H01L21/76251 ,  H01L21/76877 ,  H01L21/76898 ,  H01L21/84 ,  H01L23/3107 ,  H01L23/481 ,  H01L23/522 ,  H01L23/5225 ,  H01L23/528 ,  H01L23/552 ,  H01L24/03 ,  H01L24/05 ,  H01L27/1211 ,  H01L27/1214 ,  H01L27/1218 ,  H01L27/1266 ,  H01L29/1079 ,  H01L2221/68368 ,  H01L2224/05025

Abstract: Some embodiments of the present disclosure are directed to a device. The device includes a substrate comprising a silicon layer disposed over an insulating layer. The substrate includes a transistor device region and a radio-frequency (RF) region. An interconnect structure is disposed over the substrate and includes a plurality of metal layers disposed within a dielectric structure. A handle substrate is disposed over an upper surface of the interconnect structure. A trapping layer separates the interconnect structure and the handle substrate.

公开(公告)号：US09589831B2

公开(公告)日：2017-03-07

申请号：US14971031

申请日：2015-12-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd

Inventor： Kuo-Yu Cheng ,  Keng-Yu Chen ,  Wei-Kung Tsai ,  Kuan-Chi Tsai ,  Tsung-Yu Yang ,  Chung-Long Chang ,  Chun-Hung Chen ,  Chih-Ping Chao

IPC: H01L27/12 ,  H01L21/306 ,  H01L21/762 ,  H01L21/84

CPC classification number: H01L21/76283 ,  H01L21/7624 ,  H01L21/84 ,  H01L27/1203

Abstract: A method for forming a radio frequency area of an integrated circuit are provided. The method includes forming a buried oxide layer over a substrate, and an interface layer is formed between the substrate and the buried oxide layer. The method also includes etching through the buried oxide layer and the interface layer to form a deep trench, and a bottom surface of the deep trench is level with a bottom surface of the interface layer. The method further includes forming an implant region directly below the deep trench and forming an interlayer dielectric layer in the deep trench.

Abstract translation: 提供了一种用于形成集成电路的射频区域的方法。 该方法包括在衬底上形成掩埋氧化物层，并且在衬底和掩埋氧化物层之间形成界面层。 该方法还包括通过掩埋氧化物层和界面层蚀刻以形成深沟槽，并且深沟槽的底表面与界面层的底表面平齐。 该方法还包括在深沟槽的正下方形成植入区域，并在深沟槽中形成层间电介质层。

公开(公告)号：US09230988B2

公开(公告)日：2016-01-05

申请号：US14068353

申请日：2013-10-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Yu Cheng ,  Keng-Yu Chen ,  Wei-Kung Tsai ,  Kuan-Chi Tsai ,  Tsung-Yu Yang ,  Chung-Long Chang ,  Chun-Hung Chen ,  Chih-Ping Chao

IPC: H01L27/12 ,  H01L21/762

CPC classification number: H01L21/76283 ,  H01L21/7624 ,  H01L21/84 ,  H01L27/1203

Abstract: Embodiments of mechanisms of forming a radio frequency area of an integrated circuit are provided. The radio frequency area of an integrated circuit structure includes a substrate, a buried oxide layer formed over the substrate, and an interface layer formed between the substrate and the buried oxide layer. The radio frequency area of an integrated circuit structure also includes a silicon layer formed over the buried oxide layer and an interlayer dielectric layer formed in a deep trench. The radio frequency area of an integrated circuit structure further includes the interlayer dielectric layer extending through the silicon layer, the buried oxide layer and the interface layer. The radio frequency area of an integrated circuit structure includes an implant region formed below the interlayer dielectric layer in the deep trench and a polysilicon layer formed below the implant region.

Abstract translation: 提供了形成集成电路的射频区域的机构的实施例。 集成电路结构的射频区域包括衬底，在衬底上形成的掩埋氧化物层以及形成在衬底和掩埋氧化物层之间的界面层。 集成电路结构的射频区域还包括形成在掩埋氧化物层上的硅层和形成在深沟槽中的层间电介质层。 集成电路结构的射频区域还包括延伸穿过硅层，掩埋氧化物层和界面层的层间电介质层。 集成电路结构的射频区域包括形成在深沟槽中的层间电介质层下方的注入区域和形成在注入区域下方的多晶硅层。