公开(公告)号：US20180350739A1

公开(公告)日：2018-12-06

申请号：US15798422

申请日：2017-10-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hon-Lin Huang ,  Chen-Shien Chen ,  Chin-Yu Ku ,  Kuan-Chih Huang ,  Wei-Li Huang

IPC: H01L23/522 ,  H01L49/02 ,  H01L21/768

CPC classification number: H01L23/5227 ,  H01L21/76832 ,  H01L23/3171 ,  H01L28/10

Abstract: Semiconductor devices and methods of forming the same are disclosed. One of the semiconductor devices includes a conductive layer, a first dielectric layer, a magnetic layer and an etch stop stack. The first dielectric layer is disposed over the conductive layer. The magnetic layer is disposed over the first dielectric layer. The etch stop stack is disposed between the magnetic layer and the first dielectric layer. The etch stop stack includes a second dielectric layer and a plurality of unit layers between the second dielectric layer and the magnetic layer, and each of the plurality of unit layers comprises a tantalum layer and a tantalum oxide layer on the tantalum layer.

公开(公告)号：US11908818B2

公开(公告)日：2024-02-20

申请号：US17525593

申请日：2021-11-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Sheng-Yu Wu ,  Ching-Hui Chen ,  Mirng-Ji Lii ,  Kai-Di Wu ,  Chien-Hung Kuo ,  Chao-Yi Wang ,  Hon-Lin Huang ,  Zi-Zhong Wang ,  Chun-Mao Chiu

IPC: H01L23/00

CPC classification number: H01L24/13 ,  H01L24/08 ,  H01L24/11 ,  H01L2224/1147 ,  H01L2224/13144 ,  H01L2224/13155 ,  H01L2924/13091 ,  H01L2924/13091 ,  H01L2924/00012

Abstract: A semiconductor device includes a semiconductor substrate, a conductive pad over the semiconductor substrate, a conductive bump, a conductive cap over the conductive bump, and a passivation layer. The conductive pad is over the semiconductor substrate. The conductive bump is over the conductive pad, wherein the conductive bump has a stepped sidewall structure including a lower sidewall, an upper sidewall laterally offset from the lower sidewall, and an intermediary surface laterally extending from a bottom edge of the upper sidewall to a top edge of the lower sidewall. The conductive cap is over the conductive bump. The passivation layer is over the semiconductor substrate and laterally surrounds the conductive bump, wherein the passivation layer has a top surface higher than the intermediary surface of the stepped sidewall structure of the conductive bump and lower than a top surface of conductive cap.

公开(公告)号：US10756162B2

公开(公告)日：2020-08-25

申请号：US16260599

申请日：2019-01-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chi-Cheng Chen ,  Wei-Li Huang ,  Chien-Chih Kuo ,  Hon-Lin Huang ,  Chin-Yu Ku ,  Chen-Shien Chen

IPC: H01L49/02 ,  H01F41/04 ,  H01L23/00 ,  H01L21/768 ,  H01L23/31 ,  H01L23/532

Abstract: A structure and a formation method of a semiconductor device are provided. The method includes forming an adhesive layer over a semiconductor substrate and forming a magnetic element over the adhesive layer. The method also includes forming an isolation element extending across the magnetic element. The isolation element partially covers the top surface of the magnetic element and partially covers sidewall surfaces of the magnetic element. The method further includes partially removing the adhesive layer such that an edge of the adhesive layer is laterally disposed between an edge of the magnetic element and an edge of the isolation element. In addition, the method includes forming a conductive line over the isolation element.

公开(公告)号：US10263064B2

公开(公告)日：2019-04-16

申请号：US15638387

申请日：2017-06-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chin-Yu Ku ,  Chien-Chih Chou ,  Chen-Shien Chen ,  Hon-Lin Huang ,  Chi-Cheng Chen ,  Kuang-Yi Wu

IPC: H01L23/522 ,  H01L49/02 ,  H01L23/00

Abstract: Semiconductor devices and methods of forming the same are disclosed. One of the semiconductor device includes an inductor structure, and the inductor structure is on a substrate and includes a first metal layer, a magnetic stack, a polymer layer and a second metal layer. The first metal layer is over the substrate. The magnetic stack is over the first metal layer and has a substantially zigzag shaped sidewall. The polymer layer is over the first metal layer and encapsulates the magnetic stack. The second metal layer is over the polymer layer.

公开(公告)号：US20190051545A1

公开(公告)日：2019-02-14

申请号：US16159709

申请日：2018-10-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Wei Lu ,  Hon-Lin Huang ,  Hung-Chih Wang

IPC: H01L21/67 ,  H01L21/673 ,  B05C11/06 ,  C23C18/16

CPC classification number: H01L21/67196 ,  B05C11/06 ,  C23C18/1691 ,  H01L21/67109 ,  H01L21/67201 ,  H01L21/67303

Abstract: A semiconductor processing station including a central transfer chamber, a load lock chamber disposed adjacent to the central transfer chamber, and a cooling stage disposed adjacent to the load lock chamber and the central transfer chamber is provided. The load lock chamber is adapted to contain a wafer carrier including a plurality of wafers. The central transfer chamber communicates between the cooling stage and the load lock chamber to transfer a wafer of the plurality of wafers between the cooling stage and the load lock chamber.

公开(公告)号：US20190027452A1

公开(公告)日：2019-01-24

申请号：US15652251

申请日：2017-07-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chin-Yu Ku ,  Cheng-Lung Yang ,  Chen-Shien Chen ,  Hon-Lin Huang ,  Chao-Yi Wang ,  Ching-Hui Chen ,  Chien-Hung Kuo

IPC: H01L23/00 ,  H01L21/78 ,  H01L21/683

Abstract: A semiconductor device and a manufacturing method for the semiconductor device are provided. The semiconductor device includes a first dielectric layer, a bump, an etching stop layer and a spacer. The first dielectric layer is disposed over and exposes a conductive structure. The bump is partially disposed in the first dielectric layer to electrically connect the conductive structure. The etching stop layer is disposed over the first dielectric layer aside the bump a spacer and surrounds the bump and disposed between the etching stop layer and the bump.

公开(公告)号：US10103042B2

公开(公告)日：2018-10-16

申请号：US15009833

申请日：2016-01-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Wei Lu ,  Hon-Lin Huang ,  Hung-Chih Wang

IPC: B05C13/00 ,  H01L21/67 ,  C23C18/16 ,  B05C11/06 ,  H01L21/673

Abstract: A chamber includes a sidewall, a cooling pipe, and an external pipe. The cooling pipe includes a first segment extending along the sidewall of the chamber, and includes multiple purge nozzles. The external pipe extends to inside the chamber and is connected to the first segment of the cooling pipe. A semiconductor processing station includes a central transfer chamber, a load lock chamber, and a cooling stage. The load lock chamber and the cooling stage are disposed adjacent to the central transfer chamber. The load lock chamber is adapted to contain a wafer carrier having multiple wafers. The central transfer chamber communicates between the cooling stage and the load lock chamber to transfer a wafer between the cooling stage and the load lock chamber. A semiconductor process using the semiconductor processing station is also provided.

公开(公告)号：US20180026031A1

公开(公告)日：2018-01-25

申请号：US15714226

申请日：2017-09-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： I-Tseng Chen ,  Hon-Lin Huang ,  Chun-Hsien Huang ,  Yu-Hung Lin

IPC: H01L27/06 ,  H01L21/02 ,  H01L21/8234 ,  H01L49/02

CPC classification number: H01L27/0629 ,  H01L21/02271 ,  H01L21/823437 ,  H01L28/20

Abstract: A method for forming a semiconductor device structure is provided. The method includes providing a substrate. The method includes transferring the substrate from a stage to a deposition chamber, and no heating operation is performed on the stage. The method also includes depositing a resistor layer on the substrate. The resistor layer may have a major structure that is amorphous.

公开(公告)号：US11387168B2

公开(公告)日：2022-07-12

申请号：US16925332

申请日：2020-07-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Lung Yang ,  Chih-Hung Su ,  Chen-Shien Chen ,  Hon-Lin Huang ,  Kun-Ming Tsai ,  Wei-Je Lin

IPC: H01L23/48 ,  H01L23/00 ,  H01L23/528 ,  H01L21/48

Abstract: A semiconductor device includes a first conductive layer, an organic layer and a silicon layer. The first conductive layer includes a first surface. The organic layer is disposed over the first surface of the first conductive layer. The silicon layer is disposed over the organic layer and extended onto and in contact with the first surface of the first conductive layer.

公开(公告)号：US11329124B2

公开(公告)日：2022-05-10

申请号：US16907699

申请日：2020-06-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chin-Yu Ku ,  Chi-Cheng Chen ,  Hon-Lin Huang ,  Wei-Li Huang ,  Chun-Yi Wu ,  Chen-Shien Chen

IPC: H01L49/02

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate and a magnetic element over the semiconductor substrate. The semiconductor device structure also includes an isolation element over the magnetic element. The isolation element partially covers a top surface of the magnetic element. The semiconductor device structure further includes a conductive line over the isolation element. In addition, the semiconductor device structure includes a dielectric layer over the conductive line and the magnetic element.