公开(公告)号：US11895836B2

公开(公告)日：2024-02-06

申请号：US17022390

申请日：2020-09-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Chih-Ren Hsieh ,  Chen-Chin Liu ,  Chih-Pin Huang

IPC: H10B41/10 ,  H10B41/50 ,  H01L29/423 ,  H01L29/51 ,  H01L21/033 ,  H01L21/321 ,  H01L21/308 ,  H01L21/28 ,  H10B41/41 ,  H10B43/35 ,  H10B43/40 ,  H10B43/50

CPC classification number: H10B41/50 ,  H01L21/0337 ,  H01L21/3086 ,  H01L21/3212 ,  H01L29/40117 ,  H01L29/42328 ,  H01L29/518 ,  H10B41/10 ,  H10B41/41 ,  H10B43/35 ,  H10B43/40 ,  H10B43/50

Abstract: Some embodiments of the present application are directed towards an integrated circuit (IC). The integrated circuit includes a semiconductor substrate having a peripheral region and a memory cell region separated by an isolation structure. The isolation structure extends into a top surface of the semiconductor substrate and comprises dielectric material. A logic device is arranged on the peripheral region. A memory device is arranged on the memory region. The memory device includes a gate electrode and a memory hardmask over the gate electrode. An anti-dishing structure is disposed on the isolation structure. An upper surface of the anti-dishing structure and an upper surface of the memory hardmask have equal heights as measured from the top surface of the semiconductor substrate.

公开(公告)号：US11239246B2

公开(公告)日：2022-02-01

申请号：US16848921

申请日：2020-04-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Chih-Ren Hsieh ,  Wei Cheng Wu ,  Chih-Pin Huang

IPC: H01L27/11548 ,  H01L29/423 ,  H01L21/768 ,  H01L29/66 ,  H01L21/033 ,  H01L23/532 ,  H01L27/11524 ,  H01L21/762 ,  H01L21/321 ,  H01L27/11534 ,  H01L29/51 ,  H01L27/11575 ,  H01L21/8234

Abstract: Various embodiments of the present application are directed to a method of forming an integrated circuit (IC). An isolation structure is formed between a logic region and a memory region of a substrate. A dummy structure is formed on the isolation structure and defines a dummy sidewall of the dummy structure facing the logic region. A boundary sidewall spacer is formed covering the dummy structure and at least partially defines a boundary sidewall of the boundary sidewall spacer facing the logic region. A protecting dielectric layer is formed on a top surface of the boundary sidewall spacer by converting an uppermost portion of the boundary sidewall spacer to the protecting dielectric layer. The protecting dielectric layer is removed, and a logic device structure is formed on the logic region.

公开(公告)号：US11239245B2

公开(公告)日：2022-02-01

申请号：US16800167

申请日：2020-02-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yong-Sheng Huang ,  Ming Chyi Liu ,  Chih-Pin Huang

IPC: H01L27/11521 ,  H01L23/528 ,  H01L23/522 ,  H01L29/788 ,  H01L21/768 ,  H01L29/66 ,  H01L21/311 ,  H01L21/762 ,  H01L21/3213 ,  H01L21/28 ,  H01L29/423

Abstract: Various embodiments of the present disclosure are directed towards a method for opening a source line in a memory device. An erase gate line (EGL) and the source line are formed elongated in parallel. The source line underlies the EGL and is separated from the EGL by a dielectric layer. A first etch is performed to form a first opening through the EGL and stops on the dielectric layer. A second etch is performed to thin the dielectric layer at the first opening, wherein the first and second etches are performed with a common mask in place. A silicide process is performed to form a silicide layer on the source line at the first opening, wherein the silicide process comprises a third etch with a second mask in place and extends the first opening through the dielectric layer. A via is formed extending through the EGL to the silicide layer.

公开(公告)号：US11239089B2

公开(公告)日：2022-02-01

申请号：US16716151

申请日：2019-12-16

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Meng-Han Lin ,  Chih-Ren Hsieh ,  Chih-Pin Huang ,  Ching-Wen Chan

IPC: H01L21/3105 ,  H01L27/11521 ,  H01L21/308 ,  H01L21/762

Abstract: A method for manufacturing a semiconductor device is provided. The method includes forming a first isolation feature in a peripheral region of a substrate; recessing the cell region of the substrate after forming the first isolation feature; forming a second isolation feature in a cell region of the substrate after recessing the cell region of the substrate; forming a plurality of control gates over the cell region of the substrate; and forming a gate stack over the peripheral region of the substrate.

公开(公告)号：US11088040B2

公开(公告)日：2021-08-10

申请号：US16578303

申请日：2019-09-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Chih-Ren Hsieh ,  Ya-Chen Kao ,  Chen-Chin Liu ,  Chih-Pin Huang

IPC: H01L21/66 ,  H01L27/11529 ,  H01L27/11524 ,  H01L27/11526 ,  H01L29/423 ,  H01L27/11519

Abstract: Various embodiments of the present application are directed to an integrated circuit (IC) comprising a floating gate test device with a cell-like top layout, as well as a method for forming the IC. In some embodiments, the IC comprises a semiconductor substrate and the floating gate test device. The floating gate test device is on the semiconductor substrate, and comprises a floating gate electrode and a control gate electrode overlying the floating gate electrode. The floating gate electrode and the control gate electrode partially define an array of islands, and further partially define a plurality of bridges interconnecting the islands. The islands and the bridges define the cell-like top layout and may, for example, prevent process-induced damage to the floating gate test device.

公开(公告)号：US20200243552A1

公开(公告)日：2020-07-30

申请号：US16848921

申请日：2020-04-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Chih-Ren Hsieh ,  Wei Cheng Wu ,  Chih-Pin Huang

IPC: H01L27/11548 ,  H01L21/321 ,  H01L21/762 ,  H01L27/11524 ,  H01L23/532 ,  H01L21/033 ,  H01L29/66 ,  H01L21/768 ,  H01L29/423

Abstract: Various embodiments of the present application are directed to a method of forming an integrated circuit (IC). An isolation structure is formed between a logic region and a memory region of a substrate. A dummy structure is formed on the isolation structure and defines a dummy sidewall of the dummy structure facing the logic region. A boundary sidewall spacer is formed covering the dummy structure and at least partially defines a boundary sidewall of the boundary sidewall spacer facing the logic region. A protecting dielectric layer is formed on a top surface of the boundary sidewall spacer by converting an uppermost portion of the boundary sidewall spacer to the protecting dielectric layer. The protecting dielectric layer is removed, and a logic device structure is formed on the logic region.

公开(公告)号：US20200083126A1

公开(公告)日：2020-03-12

申请号：US16682210

申请日：2019-11-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Chih-Ren Hsieh ,  Ya-Chen Kao ,  Chen-Chin Liu ,  Chih-Pin Huang

IPC: H01L21/66 ,  H01L27/11529 ,  H01L27/11524 ,  H01L27/11526 ,  H01L29/423

Abstract: Various embodiments of the present application are directed to an integrated circuit (IC) comprising a floating gate test device with a cell-like top layout, as well as a method for forming the IC. In some embodiments, the IC comprises a semiconductor substrate and the floating gate test device. The floating gate test device is on the semiconductor substrate, and comprises a floating gate electrode and a control gate electrode overlying the floating gate electrode. The floating gate electrode and the control gate electrode partially define an array of islands, and further partially define a plurality of bridges interconnecting the islands. The islands and the bridges define the cell-like top layout and may, for example, prevent process-induced damage to the floating gate test device.

公开(公告)号：US20190088561A1

公开(公告)日：2019-03-21

申请号：US15962177

申请日：2018-04-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Chih-Ren Hsieh ,  Ya-Chen Kao ,  Chen-Chin Liu ,  Chih-Pin Huang

IPC: H01L21/66 ,  H01L27/11524 ,  H01L27/11519 ,  H01L27/11529

CPC classification number: H01L22/34 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11529 ,  H01L29/42328

Abstract: Various embodiments of the present application are directed to an integrated circuit (IC) comprising a floating gate test device with a cell-like top layout, as well as a method for forming the IC. In some embodiments, the IC comprises a semiconductor substrate and the floating gate test device. The floating gate test device is on the semiconductor substrate, and comprises a floating gate electrode and a control gate electrode overlying the floating gate electrode. The floating gate electrode and the control gate electrode partially define an array of islands, and further partially define a plurality of bridges interconnecting the islands. The islands and the bridges define the cell-like top layout and may, for example, prevent process-induced damage to the floating gate test device.