公开(公告)号：US20180177055A1

公开(公告)日：2018-06-21

申请号：US15621646

申请日：2017-06-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Siao-Shan Wang ,  Cheng-Han WU ,  Ching-Yu CHANG ,  Chin-Hsiang LIN

IPC: H05K3/06 ,  G03F7/09 ,  H01L21/027 ,  G03F7/00 ,  G03F7/20

Abstract: Provided is a material composition and method that includes forming a patterned resist layer on a substrate. The patterned resist layer has a first pattern width, and the patterned resist layer has a first pattern profile having a first proportion of active sites. In some examples, the patterned resist layer is coated with a treatment material. In some embodiments, the treatment material bonds to surfaces of the patterned resist layer to provide a treated patterned resist layer having a second pattern profile with a second proportion of active sites greater than the first proportion of active sites. By way of example, and as part of the coating the patterned resist layer with the treatment material, a first pattern shrinkage process may be performed, where the treated patterned resist layer has a second pattern width less than a first pattern width.

公开(公告)号：US20180174830A1

公开(公告)日：2018-06-21

申请号：US15628355

申请日：2017-06-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Siao-Shan WANG ,  Cheng-Han WU ,  Ching-Yu CHANG ,  Chin-Hsiang LIN

IPC: H01L21/027 ,  H01L21/033 ,  G03F7/20 ,  H01L21/308 ,  H01L21/311

Abstract: Provided is a material composition and method that includes forming a patterned resist layer on a substrate, where the patterned resist layer has a first line width roughness. In various embodiments, the patterned resist layer is coated with a treatment material, where a first portion of the treatment material bonds to surfaces of the patterned resist layer. In some embodiments, a second portion of the treatment material (e.g., not bonded to surfaces of the patterned resist layer) is removed, thereby providing a treated patterned resist layer, where the treated patterned resist layer has a second line width roughness less than the first line width roughness.

公开(公告)号：US20180138050A1

公开(公告)日：2018-05-17

申请号：US15352218

申请日：2016-11-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tzu-Yang LIN ,  Ming-Hui WENG ,  Cheng-Han WU ,  Chin-Hsiang LIN

IPC: H01L21/311 ,  H01L21/3105 ,  H01L21/027 ,  H01L29/06 ,  H01L23/528 ,  H01L21/768

CPC classification number: H01L21/76816 ,  H01L21/0274 ,  H01L21/0276 ,  H01L21/31055

Abstract: Topographic planarization methods for a lithography process are provided. The method includes providing a substrate having a topography surface. A planarization stack is formed over the topography surface of the substrate. The optical material stack includes a first optical material layer and an overlying second optical material layer, and the first optical material layer has a higher etching rate than the second optical material layer with respect to an etchant. The planarization stack is etched using the etchant to entirely remove the second optical material layer and partially remove the first optical material layer, such that the remaining first optical material layer has a substantially planar surface over the topography surface of the substrate.

公开(公告)号：US20240087945A1

公开(公告)日：2024-03-14

申请号：US18516703

申请日：2023-11-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsai-Hao HUNG ,  Ping-Cheng KO ,  Tzu-Yang LIN ,  Fang-Yu LIU ,  Cheng-Han WU

IPC: H01L21/687 ,  H01L21/66 ,  H01L21/67 ,  H01L21/677 ,  H05F1/00

CPC classification number: H01L21/68757 ,  H01L21/67167 ,  H01L21/67173 ,  H01L21/6719 ,  H01L21/67196 ,  H01L21/67201 ,  H01L21/67242 ,  H01L21/67742 ,  H01L22/10 ,  H05F1/00

Abstract: Semiconductor processing apparatuses and methods are provided in which an electrostatic discharge (ESD) prevention layer is utilized to prevent or reduce ESD events from occurring between a semiconductor wafer and one or more components of the apparatuses. In some embodiments, a semiconductor processing apparatus includes a wafer handling structure that is configured to support a semiconductor wafer during processing of the semiconductor wafer. The apparatus further includes an ESD prevention layer on the wafer handling structure. The ESD prevention layer includes a first material and a second material, and the second material has an electrical conductivity that is greater than an electrical conductivity of the first material.

公开(公告)号：US20230099053A1

公开(公告)日：2023-03-30

申请号：US17737821

申请日：2022-05-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tzu-Yang LIN ,  Chen-Yu LIU ,  Cheng-Han WU ,  Ching-Yu CHANG

IPC: H01L21/768 ,  H01L21/02 ,  H01L21/3213

Abstract: The present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In an embodiment, portions of an adhesion layer, barrier layer and/or seed layer is protected by a layer of an organic mask material as portions of the adhesion layer, barrier layer and/or seed layer are removed. The layer of organic mask material is modified to improve its resistance to penetration by wet etchants used to remove exposed portions of the adhesion layer, barrier layer and/or seed layer. An example modification includes treating the layer of organic mask material with a surfactant that is absorbed into the layer of organic mask material.

公开(公告)号：US20220320086A1

公开(公告)日：2022-10-06

申请号：US17848875

申请日：2022-06-24

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Cheng-Han WU ,  Chie-Iuan LIN ,  Kuei-Ming CHANG ,  Rei-Jay HSIEH

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/66 ,  H01L27/092 ,  H01L21/8238

Abstract: A method includes forming a semiconductor fin over a substrate; forming first, second, and third gate structures crossing the semiconductor fin; forming first source/drain epitaxy structures over the semiconductor fin and on opposite sides of the first gate structure and forming second source/drain epitaxy structures over the semiconductor fin and on opposite sides of the second gate structure, wherein bottom of the first source/drain epitaxy structures and bottom of the second source/drain epitaxy structures are lower than a top surface of the semiconductor fin; removing the third gate structure to expose the top surface of the semiconductor fin; forming an isolation structure in the semiconductor fin, wherein a bottom of the isolation structure is lower than the bottom of the first source/drain epitaxy structures and the bottom the second source/drain epitaxy structures.

公开(公告)号：US20200044072A1

公开(公告)日：2020-02-06

申请号：US16199906

申请日：2018-11-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Ho CHIANG ,  Cheng-Han WU ,  Jyh-Huei CHEN ,  Jhon-Jhy LIAW

IPC: H01L29/78 ,  H01L29/417 ,  H01L29/66

Abstract: A FinFET device structure is provided. The FinFET device structure includes a fin structure formed over a substrate and a gate structure formed over the fin structure. The FinFET device structure also includes a contact formed over the fin structure and adjacent to the gate structure. The FinFET device structure further includes a first hard mask layer formed over the gate structure, and an upper portion of the first hard mask layer has an inverted-T shape. In addition, the FinFET device structure includes a second hard mask layer formed over the contact, and the second hard mask layer has a T shape.

公开(公告)号：US20190122940A1

公开(公告)日：2019-04-25

申请号：US16221740

申请日：2018-12-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuei-Ming CHANG ,  Rei-Jay HSIEH ,  Cheng-Han WU ,  Chie-Iuan LIN

IPC: H01L21/8238 ,  H01L21/762 ,  H01L29/78 ,  H01L29/66 ,  H01L27/092 ,  H01L29/08 ,  H01L29/06

Abstract: A device includes a semiconductor fin, a first source/drain feature, a second source/drain feature, and a dielectric plug. The first source/drain feature adjoins the semiconductor fin. The second source/drain feature adjoins the semiconductor fin. The dielectric plug extends from above the semiconductor fin into the semiconductor fin, the dielectric plug is between the first source/drain feature and the second source/drain feature. The dielectric plug includes a waist and a first portion below the waist, and a width of the waist is less than a width of the first portion of the dielectric plug.

公开(公告)号：US20180277536A1

公开(公告)日：2018-09-27

申请号：US15628728

申请日：2017-06-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Cheng-Han WU ,  Chie-Iuan LIN ,  Kuei-Ming CHANG ,  Rei-Jay HSIEH

IPC: H01L27/088 ,  H01L21/8234

Abstract: A semiconductor device includes a substrate; a first gate stack disposed on the substrate; a second gate stack disposed on the substrate, wherein a metal component of the first gate stack is different from a metal component of the second gate stack; and a dielectric structure disposed over the substrate and between the first gate stack and the second gate stack, in which the dielectric structure is separated from the first gate stack and the second gate stack, and a distance between the dielectric structure and the first gate stack is substantially equal to a distance between the dielectric structure and the second gate stack.

公开(公告)号：US20210341844A1

公开(公告)日：2021-11-04

申请号：US17378507

申请日：2021-07-16

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Ming-Hui WENG ,  Chen-Yu LIU ,  Cheng-Han WU ,  Ching-Yu CHANG ,  Chin-Hsiang LIN

IPC: G03F7/40 ,  G03F7/20 ,  G03F1/82 ,  G03F7/30 ,  G03F7/32

Abstract: A method includes illuminating radiation to a resist layer over a substrate to pattern the resist layer. The patterned resist layer is developed by using a positive tone developer. The patterned resist layer is rinsed using a basic aqueous rinse solution. A pH value of the basic aqueous rinse solution is lower than a pH value of the developer, and a rinse temperature of rinsing the patterned resist layer is in a range of about 20° C. to about 40° C.