公开(公告)号：US20240320013A1

公开(公告)日：2024-09-26

申请号：US18731784

申请日：2024-06-03

Applicant: Texas Instruments Incorporated

Inventor： Mark Edward Wentroble ,  Anant Shankar Kamath ,  Rakesh Hariharan ,  Prajwala P ,  Suzanne Mary Vining

IPC: G06F9/4401 ,  G06F1/3215 ,  G06F13/38 ,  G06F13/42

CPC classification number: G06F9/4411 ,  G06F1/3215 ,  G06F13/382 ,  G06F13/4282 ,  G06F2213/0042

Abstract: A serial bus repeater includes first and second ports adapted to be coupled to respective devices. A first termination resistor network couples to the first port. A second termination resistor network couples to the second port. A squelch detect circuit couples to the first bus port and is configured to detect activity on the first bus and to generate a squelch signal responsive to detection of activity on the first port. A first state machine is configured to: determine an elapsed time during which the squelch signal indicates activity on the first port; determine that the elapsed time exceeds a first threshold; and, responsive to the determination that the elapsed time exceeds the first threshold, assert configuration signals to reconfigure the first and second termination resistor networks.

公开(公告)号：US20240028540A1

公开(公告)日：2024-01-25

申请号：US18371490

申请日：2023-09-22

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Mark E. Wentroble ,  Suzanne M. Vining ,  Rakesh Hariharan ,  Anant Kamath ,  Prajwala Puttappa

IPC: G06F13/38 ,  G06F9/4401 ,  G06F13/42

CPC classification number: G06F13/382 ,  G06F9/4413 ,  G06F13/4282 ,  G06F2213/0042

Abstract: Various configurations of high-speed data communication devices, e.g., repeaters, interfacing between a host and a peripheral, and methods of operating the same, are provided to improve the Remote Wake sequence. Repeaters include circuitry to detect the start of Resume signaling or the end of Resume, following initiation of Remote Wake. In an example, pull-up resistors coupled to upstream differential signal lines and a detection circuit with a current source are controlled to detect the start of Resume signaling. In another example, the upstream-side pull-resistors and an enable signal to an upstream-side transmitter are controlled to detect the end of Resume.

公开(公告)号：US20230237002A1

公开(公告)日：2023-07-27

申请号：US17581202

申请日：2022-01-21

Applicant: Texas Instruments Incorporated

Inventor： Anant Kamath ,  Suzanne M. Vining ,  Rakesh Hariharan ,  Mark Wentroble ,  Christopher Rodrigues ,  Prajwala P

IPC: G06F13/38 ,  G06F13/40

CPC classification number: G06F13/385 ,  G06F13/4068 ,  G06F2213/0042

Abstract: An example apparatus includes: a pullup circuit coupled to a first USB terminal; a first pulldown circuit coupled to the first USB terminal; a second pulldown circuit coupled to a second USB terminal; a third pulldown circuit coupled to a third USB terminal; a fourth pulldown circuit coupled to a fourth USB terminal; a high-speed termination detection circuit including: a current source including a first supply terminal and a second supply terminal, the first supply terminal coupled to the first USB terminal, the second supply terminal coupled to the second USB terminal; a first comparator including a first comparator terminal and a second comparator terminal, the first comparator terminal coupled to the first USB terminal; and a second comparator including a third comparator terminal and a fourth comparator terminal, the third comparator terminal coupled to the second USB terminal; and a controller including a first control terminal and a second control terminal, the first control terminal coupled to the second comparator terminal, the second control terminal coupled to the fourth comparator terminal.

公开(公告)号：US20220200599A1

公开(公告)日：2022-06-23

申请号：US17463829

申请日：2021-09-01

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Rakesh Hariharan ,  Sumantha Manoor Madhyastha

IPC: H03K19/177 ,  H03K21/08 ,  G06F1/08

Abstract: An system-on-a-chip (“SoC”) is provided. In some examples, the SoC includes a processor and a plurality of timer circuit blocks including at least a first timer circuit block and a second timer circuit block. Each of the plurality of timer circuit blocks may be selectively coupled by at least one of a first programmable matrix and a second programmable matrix. In some examples, the first programmable matrix may be configured to couple a second trigger input of the first timer circuit block with a first trigger output of the second timer circuit block. In some examples, the second programmable matrix is configured to couple a second fault input of the first timer circuit block with a first fault output of the second timer circuit block.

公开(公告)号：US20250139038A1

公开(公告)日：2025-05-01

申请号：US19004860

申请日：2024-12-30

Applicant: Texas Instruments Incorporated

Inventor： Anant Kamath ,  Suzanne M. Vining ,  Rakesh Hariharan ,  Mark Wentroble ,  Christopher Rodrigues ,  Prajwala P

IPC: G06F13/38 ,  G06F13/40

Abstract: An example apparatus includes: a pullup circuit coupled to a first USB terminal; a first pulldown circuit coupled to the first USB terminal; a second pulldown circuit coupled to a second USB terminal; a third pulldown circuit coupled to a third USB terminal; a fourth pulldown circuit coupled to a fourth USB terminal; a high-speed termination detection circuit including: a current source including a first supply terminal and a second supply terminal, the first supply terminal coupled to the first USB terminal, the second supply terminal coupled to the second USB terminal; a first comparator including a first comparator terminal and a second comparator terminal, the first comparator terminal coupled to the first USB terminal; and a second comparator including a third comparator terminal and a fourth comparator terminal, the third comparator terminal coupled to the second USB terminal; and a controller including a first control terminal and a second control terminal, the first control terminal coupled to the second comparator terminal, the second control terminal coupled to the fourth comparator terminal.

公开(公告)号：US12216602B2

公开(公告)日：2025-02-04

申请号：US17581202

申请日：2022-01-21

Applicant: Texas Instruments Incorporated

Inventor： Anant Kamath ,  Suzanne M. Vining ,  Rakesh Hariharan ,  Mark Wentroble ,  Christopher Rodrigues ,  Prajwala P

IPC: G06F13/38 ,  G06F13/40

Abstract: An example apparatus includes: a pullup circuit coupled to a first USB terminal; a first pulldown circuit coupled to the first USB terminal; a second pulldown circuit coupled to a second USB terminal; a third pulldown circuit coupled to a third USB terminal; a fourth pulldown circuit coupled to a fourth USB terminal; a high-speed termination detection circuit including: a current source including a first supply terminal and a second supply terminal, the first supply terminal coupled to the first USB terminal, the second supply terminal coupled to the second USB terminal; a first comparator including a first comparator terminal and a second comparator terminal, the first comparator terminal coupled to the first USB terminal; and a second comparator including a third comparator terminal and a fourth comparator terminal, the third comparator terminal coupled to the second USB terminal; and a controller including a first control terminal and a second control terminal, the first control terminal coupled to the second comparator terminal, the second control terminal coupled to the fourth comparator terminal.

公开(公告)号：US11803497B2

公开(公告)日：2023-10-31

申请号：US17709812

申请日：2022-03-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Mark E. Wentroble ,  Suzanne M. Vining ,  Rakesh Hariharan ,  Anant Kamath ,  Prajwala Puttappa

IPC: G06F13/38 ,  G06F9/4401 ,  G06F13/42

CPC classification number: G06F13/382 ,  G06F9/4413 ,  G06F13/4282 ,  G06F2213/0042

Abstract: Various configurations of high-speed data communication devices, e.g., repeaters, interfacing between a host and a peripheral, and methods of operating the same, are provided to improve the Remote Wake sequence. Repeaters include circuitry to detect the start of Resume signaling or the end of Resume, following initiation of Remote Wake. In an example, pull-up resistors coupled to upstream differential signal lines and a detection circuit with a current source are controlled to detect the start of Resume signaling. In another example, the upstream-side pull-resistors and an enable signal to an upstream-side transmitter are controlled to detect the end of Resume.

公开(公告)号：US11671138B2

公开(公告)日：2023-06-06

申请号：US17489483

申请日：2021-09-29

Applicant: Texas Instruments Incorporated

Inventor： RR Manikandan ,  Kumar Anurag Shrivastava ,  Robert Floyd Payne ,  Anant Shankar Kamath ,  Swaminathan Sankaran ,  Kishalay Datta ,  Siraj Akhtar ,  Mark Edward Wentroble ,  Suvadip Banerjee ,  Rakesh Hariharan ,  Gurumurti Kailaschandra Avhad

IPC: H03K5/24 ,  H04B1/44 ,  H03K3/017 ,  H04L27/06 ,  H04L27/04

CPC classification number: H04B1/44 ,  H03K3/017 ,  H03K5/24 ,  H04L27/04 ,  H04L27/066

Abstract: In described examples, an integrated circuit includes an on-off keying (OOK) digital isolator, which includes a first circuitry, a multiplexer, an OOK modulator, an isolation barrier, an OOK envelope detector, and a second circuitry. The first circuitry generates and outputs a calibration signal. The multiplexer has a data signal input, and an input coupled to a first circuitry output. An OOK modulator input is coupled to a multiplexer output. An isolation barrier input is coupled to an OOK modulator output. An OOK envelope detector input is coupled to an isolation barrier output. The second circuitry includes an input coupled to an OOK envelope detector output, and an output coupled to an OOK envelope detector control input. The second circuitry detects a duty cycle distortion (DCD) of the OOK envelope detector output, and outputs a control signal to change the OOK envelope detector output's duty cycle based on the detected DCD.

公开(公告)号：US11133804B1

公开(公告)日：2021-09-28

申请号：US17127167

申请日：2020-12-18

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Rakesh Hariharan ,  Sumantha Manoor Madhyastha

IPC: H03K19/177 ,  G06F1/08 ,  H03K21/08 ,  G06F115/02

Abstract: An system-on-a-chip (“SoC”) is provided. In some examples, the SoC includes a processor and a plurality of timer circuit blocks including at least a first timer circuit block and a second timer circuit block. Each of the plurality of timer circuit blocks may be selectively coupled by at least one of a first programmable matrix and a second programmable matrix. In some examples, the first programmable matrix may be configured to couple a second trigger input of the first timer circuit block with a first trigger output of the second timer circuit block. In some examples, the second programmable matrix is configured to couple a second fault input of the first timer circuit block with a first fault output of the second timer circuit block.