公开(公告)号：US20210005731A1

公开(公告)日：2021-01-07

申请号：US17028205

申请日：2020-09-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngtek OH ,  Jinwook JUNG ,  Hyeokshin KWON ,  Wontaek SEO ,  Insu JEON

IPC: H01L29/45 ,  H01L29/786 ,  H01L29/16

Abstract: A silicene electronic device includes a silicene material layer. The silicene material layer of the silicene electronic device has a 2D honeycomb structure of silicon atoms, is doped with at least one material of Group I, Group II, Group XVI, and Group XVII, and includes at least one of a p-type dopant region doped with a p-type dopant and an n-type dopant region doped with an n-type dopant. An electrode material layer including a material having a work function lower than the electron affinity of silicene is formed on the silicene material layer.

公开(公告)号：US20200342894A1

公开(公告)日：2020-10-29

申请号：US16715721

申请日：2019-12-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Boreum JEONG ,  Wontaek SEO ,  Youngtek OH ,  Yunju YU ,  Moonil JUNG

IPC: G10L25/51 ,  G10L21/0272 ,  G10L15/22

Abstract: Provided is a sound source tracking apparatuses including a vibration unit including vibrators configured to vibrate in response to an ambient sound, the ambient sound including individual sounds, and a processor configured to separate the ambient sound into individual sounds, to determine a target individual sound having a target tone color among the individual sounds, and to obtain a relative location of a target sound source that generates the target individual sound.

公开(公告)号：US20250022927A1

公开(公告)日：2025-01-16

申请号：US18738877

申请日：2024-06-10

Applicant: SAMSUNG ELECTRONICS CO., LTD. ,  FOUNDATION OF SOONGSIL UNIVERSITY-INDUSTRY COOPERATION

Inventor： Youngtek OH ,  Geonwook Yoo ,  Kyungwook Hwang ,  Changkun Park ,  Sanghoon Song ,  Minjae Yeom ,  Gyuhyung Lee ,  Junsik Hwang

IPC: H01L29/417 ,  H01L29/20 ,  H01L29/66 ,  H01L29/778 ,  H01L33/00

Abstract: A semiconductor device includes a channel layer including a first group III-V semiconductor material; a barrier layer provided on an upper surface of the channel layer, the barrier layer including a second group III-V semiconductor material that is different than the first group III-V semiconductor material; a plurality of sources/drains spaced apart from each other on an upper surface of the barrier layer; a gate insulating layer covering the upper surface of the barrier layer and upper surfaces of the plurality of sources/drains; a gate provided on an upper surface of the gate insulating layer, the gate not overlapping the plurality of sources/drains; a plurality of source/drain electrodes electrically connected to corresponding sources/drains among the plurality of sources/drains; and a gate electrode electrically connected to the gate, wherein the plurality of source/drain electrodes has a diagonally symmetrical arrangement.

公开(公告)号：US20240322068A1

公开(公告)日：2024-09-26

申请号：US18433068

申请日：2024-02-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youngtek OH ,  Dongho KIM ,  Joonyong PARK ,  Junsik HWANG ,  Dongkyun KIM ,  Sanghoon SONG ,  Minchul YU ,  Kyungwook HWANG

IPC: H01L33/00 ,  H01L21/67 ,  H01L21/673

CPC classification number: H01L33/005 ,  H01L21/67132 ,  H01L21/67333

Abstract: A micro semiconductor chip transfer method is provided and includes: preparing a transfer substrate including an upper portion having grooves formed therein; supplying, to the upper portion of the transfer substrate, a suspension including micro semiconductor chips and a liquid; and aligning the micro semiconductor chips in the grooves by sweeping, with an alignment bar that includes a hydrophobic wiper, an upper surface of the transfer substrate while the suspension is on the upper surface of the transfer substrate.

公开(公告)号：US20220319602A1

公开(公告)日：2022-10-06

申请号：US17708362

申请日：2022-03-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minhyun LEE ,  Taein KIM ,  Youngtek OH ,  Hyeonjin SHIN ,  Changseok LEE

IPC: G11C16/04 ,  H01L27/1157 ,  H01L27/11524 ,  H01L27/11551 ,  H01L27/11578

Abstract: Provided is a vertical nonvolatile memory device in which a thickness of one memory cell is reduced to reduce an entire thickness of a memory cell string and increase the number of stacked memory cells. The nonvolatile memory device includes a plurality of memory cell strings. Each of the memory cell strings may include a plurality of insulating spacers each extending in a first direction, a plurality of gate electrodes each extending in the first direction and alternately arranged with the plurality of insulating spacers in a second direction perpendicular to the first direction, and a plurality of contacts respectively arranged to contact a side surface of the plurality of gate electrodes respectively corresponding to the plurality of contacts.

公开(公告)号：US20210234016A1

公开(公告)日：2021-07-29

申请号：US17227456

申请日：2021-04-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngtek OH ,  Jinwook JUNG ,  Seunggeol NAM ,  Wontaek SEO ,  Insu JEON

IPC: H01L29/45

Abstract: Provided are transistors including an electride electrode. The transistor includes a substrate, a source region and a drain region doped with ions of different polarity from the substrate in a surface of the substrate, a source electrode and a drain electrode including an electride material on the source region and the drain region, a gate insulating layer surrounding the source electrode and a drain electrode on the substrate, and a gate electrode between the source electrode and the drain electrode on the substrate. The source electrode and the drain electrode have an ohmic contact with the substrate.

公开(公告)号：US20170186934A1

公开(公告)日：2017-06-29

申请号：US15388668

申请日：2016-12-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyeokshin KWON ,  Youngtek OH ,  Insu JEON

IPC: H01L39/22 ,  G06N99/00

CPC classification number: H01L39/223 ,  G06N99/002 ,  H01L27/18

Abstract: Multi-qubit devices and quantum computers including the same are provided. The multi-qubit device may include a first layer including a plurality of qubits; a second layer that is disposed on the first layer, and comprises a plurality of flux generating elements that apply flux to the plurality of qubits, a plurality of wire patterns that provide current to the plurality of flux generating elements, and a plurality of plugs that are disposed perpendicular to the plurality of flux generating elements and the plurality of wire patterns and interconnect the plurality of flux generating elements and the plurality of wire patterns. Each of the plurality of flux generating elements may be integrated with a corresponding one of the plurality of wire patterns and a corresponding one of the plurality of plugs.

公开(公告)号：US20160104790A1

公开(公告)日：2016-04-14

申请号：US14878098

申请日：2015-10-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youngtek OH

IPC: H01L29/778 ,  H01L29/167 ,  H01L29/15

CPC classification number: H01L29/778 ,  H01L29/167 ,  H01L29/267 ,  H01L29/4232

Abstract: Provided are silicene material layers and electronic devices having a silicene material layer. The silicene material layer contains silicon atoms in a 2-dimensional honeycomb structure formed as one of a monolayer and a double layer. The silicene material layer includes a doping region doped with at least one material from the group of Group 1, Group 2, Group 16 and Group 17 and at least one of a p-type dopant or an n-type dopant.

Abstract translation: 提供有硅材料层和具有硅材料层的电子器件。 所述硅材料层在形成为单层和双层之一的2维蜂窝结构体中含有硅原子。 硅材料层包括掺杂有来自组1，组2，组16和组17的至少一种材料的掺杂区域和p型掺杂剂或n型掺杂剂中的至少一种。