公开(公告)号：US12009057B2

公开(公告)日：2024-06-11

申请号：US18143967

申请日：2023-05-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hojun Yoon ,  Youngchul Cho ,  Youngdon Choi ,  Changsik Yoo ,  Junghwan Choi

IPC: G11C7/22 ,  G11C7/10

CPC classification number: G11C7/222 ,  G11C7/1057 ,  G11C7/1084

Abstract: A semiconductor memory device includes a quadrature error correction circuit, a clock generation circuit and a data input/output (I/O) buffer. The quadrature error correction circuit performs a locking operation to generate a first corrected clock signal and a second corrected clock signal by adjusting a skew and a duty error of a first through fourth clock signals generated based on a data clock signal and performs a relocking operation to lock the second corrected clock signal to the first corrected clock signal in response to a relock signal. The clock generation circuit generates an output clock signal and a strobe signal based on the first corrected clock signal and the second corrected clock signal. The data I/O buffer generates a data signal by sampling data from a memory cell array based on the output clock signal and transmits the data signal and the strobe signal to a memory controller.

公开(公告)号：US20230307022A1

公开(公告)日：2023-09-28

申请号：US18143967

申请日：2023-05-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hojun Yoon ,  Youngchul Cho ,  Youngdon Choi ,  Changsik Yoo ,  Junghwan Choi

IPC: G11C7/22 ,  G11C7/10

CPC classification number: G11C7/222 ,  G11C7/1057 ,  G11C7/1084

Abstract: A semiconductor memory device includes a quadrature error correction circuit, a clock generation circuit and a data input/output (I/O) buffer. The quadrature error correction circuit performs a locking operation to generate a first corrected clock signal and a second corrected clock signal by adjusting a skew and a duty error of a first through fourth clock signals generated based on a data clock signal and performs a relocking operation to lock the second corrected clock signal to the first corrected clock signal in response to a relock signal. The clock generation circuit generates an output clock signal and a strobe signal based on the first corrected clock signal and the second corrected clock signal. The data I/O buffer generates a data signal by sampling data from a memory cell array based on the output clock signal and transmits the data signal and the strobe signal to a memory controller.

公开(公告)号：US11742016B2

公开(公告)日：2023-08-29

申请号：US17508598

申请日：2021-10-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hojun Yoon ,  Wonjoo Jung ,  Jaewoo Park ,  Youngchul Cho ,  Youngdon Choi ,  Junghwan Choi

IPC: G11C7/22 ,  G11C11/4076 ,  G11C29/02 ,  H03K5/156 ,  H03K5/12

CPC classification number: G11C11/4076 ,  G11C7/222 ,  G11C29/023 ,  H03K5/1565 ,  G11C29/028 ,  H03K5/12

Abstract: A quadrature error correction circuit includes a duty cycle adjusting circuit, a phase interpolator, a phase detector, and a delay control circuit. The duty cycle adjusting circuit generates a first corrected clock signal and a second corrected clock signal whose skew and duty cycle error are concurrently adjusted by adjusting a delay of edges of a second clock signal and adjusting a delay of a falling edge of a first clock signal based on first through fourth control code sets. The phase interpolator generates a second delayed and selected clock signal by delaying a second selected clock signal selected from first through fourth adjusted clock signals. A phase detector detects a phase difference between a first selected clock signal and the second delayed and selected clock signal to generate an up/down signal. The delay control circuit generates the first through fourth control code sets based on the up/down signal.

公开(公告)号：US11736097B2

公开(公告)日：2023-08-22

申请号：US17695168

申请日：2022-03-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Mingyu Lee ,  Youngchul Cho ,  Seungjin Park ,  Youngdon Choi ,  Junghwan Choi

IPC: H03K5/00 ,  H03K5/06 ,  H03K5/05 ,  H03K5/15

CPC classification number: H03K5/06 ,  H03K5/05 ,  H03K5/1506 ,  H03K5/1508

Abstract: A clock signal delay path unit includes a first delay cell including a first root signal line for delaying and transmitting a clock signal, a first repeater to transmit the clock signal transmitted through the first root signal line without signal attenuation, and a second root signal line for delaying and transmitting the clock signal output from the first repeater, a second delay cell including a first inverting circuit configured to invert the clock signal provided from the first delay cell to generate an inverted clock signal, and a third delay cell including a first branch signal line for delaying and transmitting the inverted clock signal provided from the second delay cell, a second repeater to transmit the inverted clock signal transmitted through the first branch signal line, and a second branch signal line for delaying and transmitting the inverted clock signal output from the second repeater.