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    Integrated circuit semiconductor device
    16.
    发明授权
    Integrated circuit semiconductor device 有权

    公开(公告)号：US11616118B2

    公开(公告)日：2023-03-28

    申请号：US16938286

    申请日：2020-07-24

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Seungjin Kim ,  Sungsoo Yim ,  Suklae Kim ,  Hyukwoo Kwon ,  Byunghyun Lee ,  Yoonyoung Choi

    IPC: H01L49/02 ,  H01L27/108

    Abstract: An integrated circuit semiconductor device includes a plurality of cylindrical structures separated from each other on a substrate; and a plurality of supporters having an opening region exposing side surfaces of the plurality of cylindrical structures, the plurality of supporters being in contact with the side surfaces of the plurality of cylindrical structures and supporting the plurality of cylindrical structures, wherein each of the plurality of supporters has both side surfaces having slopes and has a top width that is less than a bottom width.

    Semiconductor memory device
    17.
    发明授权
    Semiconductor memory device 有权

    公开(公告)号：US11557596B2

    公开(公告)日：2023-01-17

    申请号：US17192086

    申请日：2021-03-04

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Seoryong Park ,  Seunguk Han ,  Jiyoung Ahn ,  Kiseok Lee ,  Yoonyoung Choi ,  Jiseok Hong

    IPC: H01L27/11551 ,  H01L27/11519 ,  G11C8/14 ,  H01L27/11578 ,  G11C7/18 ,  H01L27/11565

    Abstract: A semiconductor memory device includes a substrate with a cell array region, a first interface region, and a second interface region, the cell array region being provided with active regions, bit lines on the cell array region and the second interface region, dielectric patterns on top surfaces of the bit lines and extending along the top surfaces of the bit lines and further extending onto the first interface region, a device isolation pattern on the substrate, and including a first portion on the cell array region and a second portion on the first interface region, the first portion defining the active regions, the second portion being provided with first recesses, and each first recess being disposed between two adjacent dielectric patterns, and first sacrificial semiconductor patterns disposed on the first interface region and in the first recesses. The first sacrificial semiconductor patterns include polycrystalline silicon.

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