公开(公告)号：US11776894B2

公开(公告)日：2023-10-03

申请号：US16848246

申请日：2020-04-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yeonjin Lee ,  Junyong Noh ,  Minjung Choi ,  Junghoon Han ,  Yunrae Cho

IPC: H01L23/48 ,  H01L23/485 ,  H01L23/522 ,  H01L23/532 ,  H01L23/00 ,  H01L23/31 ,  H01L21/768 ,  H01L25/065 ,  H01L21/76 ,  H01L23/525 ,  H01L21/78 ,  H01L21/82 ,  H01L23/528 ,  H01L21/56

CPC classification number: H01L23/5222 ,  H01L21/561 ,  H01L21/76832 ,  H01L21/78 ,  H01L21/82 ,  H01L23/3185 ,  H01L23/481 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53295 ,  H01L24/05 ,  H01L23/562 ,  H01L2224/024 ,  H01L2224/0237

Abstract: A semiconductor chip includes a device layer on a substrate, the device layer including a plurality of semiconductor devices; a wiring structure and a lower inter-wiring dielectric layer each on the device layer, the lower inter-wiring dielectric layer surrounding the wiring structure and having a lower permittivity than silicon oxide; an upper inter-wiring dielectric layer arranged on the lower inter-wiring dielectric layer; an isolation recess arranged along an edge of the substrate, the isolation recess formed on side surfaces of the lower and upper inter-wiring dielectric layers and having a bottom surface at a level equal to or lower than that of a bottom surface of the lower inter-wiring dielectric layer; and a cover dielectric layer covering the side surfaces of the lower and upper inter-wiring dielectric layers and the bottom surface of the isolation recess.

公开(公告)号：US20210305190A1

公开(公告)日：2021-09-30

申请号：US17146550

申请日：2021-01-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jimin Choi ,  Jung-Hoon Han ,  Yeonjin Lee ,  Jong-Min Lee ,  Jihoon Chang

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L21/66

Abstract: Semiconductor packages may include a semiconductor chip on a substrate and an under-fill layer between the semiconductor chip and the substrate. The semiconductor chip may include a semiconductor substrate including first and second regions, and an interlayer dielectric layer that may cover the semiconductor substrate and may include connection lines. First conductive pads may be on the first region and may be electrically connected to some of the connection lines. Second conductive pads may be on the second region and may be electrically isolated from all of the connection lines. The semiconductor chip may also include a passivation layer that may cover the interlayer dielectric layer and may include holes that may expose the first and second conductive pads, respectively. On the second region, the under-fill layer may include a portion that may be in one of the first holes and contact one of the second conductive pads.

公开(公告)号：US20250157948A1

公开(公告)日：2025-05-15

申请号：US19023084

申请日：2025-01-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Minjung Choi ,  Yeonjin Lee ,  Jeonil Lee ,  Jongmin Lee

IPC: H01L23/00 ,  H01L21/78 ,  H01L23/48 ,  H01L23/522 ,  H01L23/528 ,  H01L23/58

Abstract: A semiconductor device includes; a semiconductor substrate including a chip area and a scribe lane area, a low-k layer on the semiconductor substrate, an interlayer insulating layer on the low-k layer, a trench area in the scribe lane area, a gap-fill insulating layer in the trench area and vertically extending from the semiconductor substrate through the low-k layer and the interlayer insulating layer to expose an upper surface of the gap-fill insulating layer through the interlayer insulating layer, and a first metal liner covering a side surface of the gap-fill insulating layer and disposed between the gap-fill insulating layer and the low-k layer and between the gap-fill insulating layer and the interlayer insulating layer.

公开(公告)号：US12230587B2

公开(公告)日：2025-02-18

申请号：US17706013

申请日：2022-03-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Minjung Choi ,  Yeonjin Lee ,  Jeonil Lee ,  Jongmin Lee

IPC: H01L21/78 ,  H01L23/00 ,  H01L23/48 ,  H01L23/522 ,  H01L23/528 ,  H01L23/58

Abstract: A semiconductor device includes; a semiconductor substrate including a chip area and a scribe lane area, a low-k layer on the semiconductor substrate, an interlayer insulating layer on the low-k layer, a trench area in the scribe lane area, a gap-fill insulating layer in the trench area and vertically extending from the semiconductor substrate through the low-k layer and the interlayer insulating layer to expose an upper surface of the gap-fill insulating layer through the interlayer insulating layer, and a first metal liner covering a side surface of the gap-fill insulating layer and disposed between the gap-fill insulating layer and the low-k layer and between the gap-fill insulating layer and the interlayer insulating layer.

公开(公告)号：US20250053336A1

公开(公告)日：2025-02-13

申请号：US18408741

申请日：2024-01-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yeonjin Lee

IPC: G06F3/06

Abstract: A memory device configured to connect to a plurality of hosts through an interconnect device and to communicate with the plurality of hosts by a compute express link (CXL) protocol includes a command scheduler, a memory, and a priority scheduler. The command scheduler schedules commands included in requests from the plurality of hosts. The memory generates internal data by performing memory operations corresponding to the scheduled commands. The priority scheduler designates a first host from the plurality of hosts as a priority host based on attribute information of each of the plurality of hosts and generates an output data by rearranging the internal data such that a data requested by the first host is output with priority.

公开(公告)号：US11756843B2

公开(公告)日：2023-09-12

申请号：US17706401

申请日：2022-03-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minjung Choi ,  Junyong Noh ,  Yeonjin Lee ,  Junghoon Han

IPC: H01L21/00 ,  H01L21/66 ,  H01L21/78

CPC classification number: H01L22/34 ,  H01L21/78 ,  H01L22/32

Abstract: A semiconductor device includes a substrate including a first part and a second part, a memory cell disposed on the first part, an insulation layer disposed on the first part and the second part, the insulation layer covering the memory cell, a portion of the insulation layer on the second part including a stepped sidewall, and a first pattern group disposed on the second part and in the portion of the insulation layer and the substrate. A first sidewall of the semiconductor device corresponds to the stepped sidewall including an upper sidewall, a lower sidewall and a connecting surface connecting the upper sidewall to the lower sidewall. The lower sidewall disposed under the upper sidewall is closer to the substrate than the upper sidewall, and has surface roughness different from surface roughness of the upper sidewall.

公开(公告)号：US20230138616A1

公开(公告)日：2023-05-04

申请号：US18051623

申请日：2022-11-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minjung Choi ,  Jongmin Lee ,  Yeonjin Lee ,  Jeonil Lee ,  Jimin Choi

IPC: H01L21/02 ,  H01L23/14 ,  H01L23/31 ,  H01L25/065

Abstract: A semiconductor device including a semiconductor substrate, a first interlayer insulating layer arranged on the semiconductor substrate, a low dielectric layer arranged on the first interlayer insulating layer, a second interlayer insulating layer and a third interlayer insulating layer sequentially arranged on the low dielectric layer, and a through silicon via penetrating the semiconductor substrate and the first interlayer insulating layer, wherein the semiconductor substrate, the first interlayer insulating layer, and the low dielectric layer constitute a chamfered structure including a first chamfered surface parallel to the top surface of the semiconductor substrate and a second chamfered surface inclined with respect to the top surface of the semiconductor substrate and connected to the first chamfered surface may be provided.

公开(公告)号：US11557556B2

公开(公告)日：2023-01-17

申请号：US17328365

申请日：2021-05-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minjung Choi ,  Sooho Shin ,  Yeonjin Lee ,  Junghoon Han

IPC: H01L23/00 ,  H01L21/56

Abstract: A semiconductor device includes an interlayer insulating layer disposed on a substrate; a plurality of middle interconnections disposed in the interlayer insulating layer; a pad disposed on the interlayer insulating layer; an upper interconnection disposed on the interlayer insulating layer; a protective insulating layer covering an edge of the pad, the upper interconnection, and a horizontal gap between the pad and the upper interconnection, the protective insulating layer having an opening on the pad; and a bump disposed on the pad, the bump extending on the protective insulating layer and overlapping the upper interconnection from a top-down view. At least one of the plurality of middle interconnections from among middle interconnections vertically closest to the pad has a first vertical thickness, the pad has a second vertical thickness that is twice to 100 times the first vertical thickness, a length of the gap between the pad and the upper interconnection is 1 μm or more, and an upper surface of the protective insulating layer is planar.

公开(公告)号：US12288734B2

公开(公告)日：2025-04-29

申请号：US17714202

申请日：2022-04-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Juik Lee ,  Jong-Min Lee ,  Jimin Choi ,  Yeonjin Lee ,  Jeon Il Lee

IPC: H01L21/00 ,  H01L23/00 ,  H01L23/48 ,  H01L23/522 ,  H01L23/528 ,  H01L25/065 ,  H01L25/10

Abstract: A semiconductor device includes a substrate including a first side and a second side opposite to each other, a first penetrating structure that penetrates the substrate, and a second penetrating structure that penetrates the substrate, the second penetrating structure being spaced apart from the first penetrating structure, and an area of the first penetrating structure being more than twice an area of the second penetrating structure, as viewed from the first side of the substrate.

公开(公告)号：US12183660B2

公开(公告)日：2024-12-31

申请号：US17736212

申请日：2022-05-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeonil Lee ,  Jongmin Lee ,  Jimin Choi ,  Yeonjin Lee

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/532 ,  H01L23/535

Abstract: A semiconductor device includes a substrate including a first surface, and a second surface opposing the first surface. A via insulating layer extending through the substrate is disposed. A through-silicon via extending through the via insulating layer is disposed. The center of the through-silicon via is misaligned from the center of the via insulating layer. A blocking layer is disposed on the first surface. A first insulating layer is disposed on the blocking layer. A contact plug contacting the through-silicon via and extending through the first insulating layer and the blocking layer is disposed.