公开(公告)号：US12096615B2

公开(公告)日：2024-09-17

申请号：US18368939

申请日：2023-09-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wooyoung Choi ,  Juseong Oh ,  Yoosang Hwang

IPC: H01L23/522 ,  G11C5/10 ,  H01L23/528 ,  H01L49/02 ,  H10B12/00

CPC classification number: H10B12/37 ,  G11C5/10 ,  H01L23/5226 ,  H01L23/528 ,  H01L28/60

Abstract: A semiconductor device includes a substrate including a cell area having a first active region and a peripheral circuit area having a second active region, a direct contact contacting the first active region in the cell area, a bit line structure disposed on the direct contact, a capacitor structure electrically connected to the first active region, a gate structure disposed on the second active region in the peripheral circuit area, lower wiring layers disposed adjacent to the gate structure and electrically connected to the second active region, upper wiring layers disposed on the lower wiring layers, a wiring insulating layer disposed between the lower wiring layers and the upper wiring layers, and upper contact plugs connected to at least one of the lower wiring layers and the upper wiring layers and extending through the wiring insulating layer.

公开(公告)号：US11658117B2

公开(公告)日：2023-05-23

申请号：US17667866

申请日：2022-02-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taejin Park ,  Keunnam Kim ,  Sohyun Park ,  Jin-Hwan Chun ,  Wooyoung Choi ,  Sunghee Han ,  Inkyoung Heo ,  Yoosang Hwang

IPC: H01L23/48 ,  H01L23/52 ,  H01L23/528 ,  H01L29/06 ,  G11C5/10 ,  H01L29/423 ,  H01L27/108 ,  H01L21/768

CPC classification number: H01L23/528 ,  G11C5/10 ,  H01L21/76831 ,  H01L27/10888 ,  H01L29/0649 ,  H01L29/4236

Abstract: The semiconductor device provided comprises a substrate that includes active regions that extends in a first direction and a device isolation layer that defines the active regions, word lines that run across the active regions in a second direction that intersects the first direction, bit-line structures that intersect the active regions and the word lines and that extend in a third direction that is perpendicular to the second direction, first contacts between the bit-line structures and the active regions, spacer structures on sidewalls of the bit-line structures, and second contacts that are between adjacent bit-line structures and are connected to the active regions. Each of the spacer structures extends from the sidewalls of the bit-line structures onto a sidewall of the device isolation layer.

公开(公告)号：US20220165657A1

公开(公告)日：2022-05-26

申请号：US17667866

申请日：2022-02-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： TAEJIN PARK ,  Keunnam Kim ,  Sohyun Park ,  Jin-Hwan Chun ,  Wooyoung Choi ,  Sunghee Han ,  Inkyoung Heo ,  Yoosang Hwang

IPC: H01L23/528 ,  H01L29/06 ,  G11C5/10 ,  H01L29/423 ,  H01L27/108 ,  H01L21/768

Abstract: The semiconductor device provided comprises a substrate that includes active regions that extends in a first direction and a device isolation layer that defines the active regions, word lines that run across the active regions in a second direction that intersects the first direction, bit-line structures that intersect the active regions and the word lines and that extend in a third direction that is perpendicular to the second direction, first contacts between the bit-line structures and the active regions, spacer structures on sidewalls of the bit-line structures, and second contacts that are between adjacent bit-line structures and are connected to the active regions. Each of the spacer structures extends from the sidewalls of the bit-line structures onto a sidewall of the device isolation layer.

公开(公告)号：US20220139921A1

公开(公告)日：2022-05-05

申请号：US17372634

申请日：2021-07-12

Applicant: Samsung Electronics Co., Ltd

Inventor： EUNA KIM ,  Keunnam Kim ,  Kiseok Lee ,  Wooyoung Choi ,  Sunghee Han

IPC: H01L27/108 ,  H01L23/528

Abstract: A semiconductor device includes a substrate including an active region, a first bitline structure and a second bitline structure that extend side by side on the substrate, a storage node contact electrically connected to the active region between the first and second bitline structures, a lower landing pad between the first and second bitline structures and on the storage node contact, an upper landing pad in contact with the first bitline structure and electrically connected to the lower landing pad, and a capping insulating layer. A lower surface of the upper landing pad in contact with the first bitline structure and a lower surface of the capping insulating layer in contact with the lower landing pad each include a portion in which a horizontal separation distance is increased from the adjacent upper landing pad in a direction toward the substrate.

公开(公告)号：US20210082799A1

公开(公告)日：2021-03-18

申请号：US16879009

申请日：2020-05-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taejin Park ,  Keunnam Kim ,  Sohyun Park ,  Jin-Hwan Chun ,  Wooyoung Choi ,  Sunghee Han ,  Inkyoung Heo ,  Yoosang Hwang

IPC: H01L23/528 ,  H01L29/06 ,  H01L21/768 ,  H01L29/423 ,  H01L27/108 ,  G11C5/10

Abstract: The semiconductor device provided comprises a substrate that includes active regions that extends in a first direction and a device isolation layer that defines the active regions, word lines that run across the active regions in a second direction that intersects the first direction, bit-line structures that intersect the active regions and the word lines and that extend in a third direction that is perpendicular to the second direction, first contacts between the bit-line structures and the active regions, spacer structures on sidewalls of the bit-line structures, and second contacts that are between adjacent bit-line structures and are connected to the active regions. Each of the spacer structures extends from the sidewalls of the bit-line structures onto a sidewall of the device isolation layer.

公开(公告)号：US10425409B2

公开(公告)日：2019-09-24

申请号：US15436123

申请日：2017-02-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Gwiho Lee ,  Hakjoo Kim ,  Sangho Park ,  Yong-Jun Park ,  Jong-Hoon Park ,  In-Jun Son ,  Yang Soo Lee ,  Moonsu Chang ,  Ho-Dong Jwa ,  Wooyoung Choi

IPC: H04L29/06 ,  H04W12/06 ,  G06K9/00

Abstract: A method and an apparatus for providing a connection between electronic devices using authentication based on biometric information are provided. The electronic device includes: a first communication circuit to support NFC; a second communication circuit to support non-NFC; a biometric sensor; a memory to store first authentication information corresponding to an external device; and a processor. The processor is configured to: acquire connection information related to a connection with the external device from the external device using the first communication circuit in response to NFC tagging between the electronic device and the external device; establish a communication connection with the external device using the second communication circuit based on at least the connection information; receive a request for authentication information from the external device in response to the communication connection being established; acquire biometric information corresponding to a user of the electronic device using the biometric sensor in response to the request; authenticate the user based on at least the biometric information; when the authenticating succeeds, generate second authentication information based on at least the first authentication information; and transmit the second authentication information to the external device.

公开(公告)号：US20180136713A1

公开(公告)日：2018-05-17

申请号：US15814790

申请日：2017-11-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaecheol Kim ,  Jinkyu Kim ,  Dongwoo Kim ,  Jeongho Kim ,  Jaesoo Chaung ,  Jongshik Ha ,  Heetae Oh ,  Hyeokseon Yu ,  Seungyoung Lee ,  Wooyoung Choi ,  Jaewoong Han ,  Mangun Hur

IPC: G06F1/32 ,  G06F15/78 ,  H03F3/217

Abstract: An electronic device includes a system-on-chip (SoC) including at least one component, a memory, and a processor functionally connected to the SoC and the memory. The processor is configured to apply a default voltage for driving the at least one component at a specific frequency. The processor is also configured to determine whether data on an offset voltage corresponding to the at least one component and the specific frequency is stored. The processor is further configured to apply the offset voltage, being different from the default voltage, to the at least one component when the data on the offset voltage is stored. Other embodiments are possible.

公开(公告)号：US11929324B2

公开(公告)日：2024-03-12

申请号：US18133575

申请日：2023-04-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taejin Park ,  Keunnam Kim ,  Sohyun Park ,  Jin-Hwan Chun ,  Wooyoung Choi ,  Sunghee Han ,  Inkyoung Heo ,  Yoosang Hwang

IPC: H01L23/48 ,  G11C5/10 ,  H01L21/768 ,  H01L23/52 ,  H01L23/528 ,  H01L29/06 ,  H01L29/423 ,  H10B12/00

CPC classification number: H01L23/528 ,  G11C5/10 ,  H01L21/76831 ,  H01L29/0649 ,  H01L29/4236 ,  H10B12/485

Abstract: The semiconductor device provided comprises a substrate that includes active regions that extends in a first direction and a device isolation layer that defines the active regions, word lines that run across the active regions in a second direction that intersects the first direction, bit-line structures that intersect the active regions and the word lines and that extend in a third direction that is perpendicular to the second direction, first contacts between the bit-line structures and the active regions, spacer structures on sidewalls of the bit-line structures, and second contacts that are between adjacent bit-line structures and are connected to the active regions. Each of the spacer structures extends from the sidewalls of the bit-line structures onto a sidewall of the device isolation layer.

公开(公告)号：US11805639B2

公开(公告)日：2023-10-31

申请号：US17372634

申请日：2021-07-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Euna Kim ,  Keunnam Kim ,  Kiseok Lee ,  Wooyoung Choi ,  Sunghee Han

IPC: H10B12/00 ,  H01L23/528

CPC classification number: H10B12/315 ,  H01L23/528 ,  H10B12/0335 ,  H10B12/482 ,  H10B12/485

Abstract: A semiconductor device includes a substrate including an active region, a first bitline structure and a second bitline structure that extend side by side on the substrate, a storage node contact electrically connected to the active region between the first and second bitline structures, a lower landing pad between the first and second bitline structures and on the storage node contact, an upper landing pad in contact with the first bitline structure and electrically connected to the lower landing pad, and a capping insulating layer. A lower surface of the upper landing pad in contact with the first bitline structure and a lower surface of the capping insulating layer in contact with the lower landing pad each include a portion in which a horizontal separation distance is increased from the adjacent upper landing pad in a direction toward the substrate.

公开(公告)号：US11785763B2

公开(公告)日：2023-10-10

申请号：US17568440

申请日：2022-01-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wooyoung Choi ,  Juseong Oh ,  Yoosang Hwang

IPC: H01L21/768 ,  H10B12/00 ,  H01L49/02 ,  H01L23/522 ,  H01L23/528 ,  G11C5/10

CPC classification number: H10B12/37 ,  G11C5/10 ,  H01L23/528 ,  H01L23/5226 ,  H01L28/60

Abstract: A semiconductor device includes a substrate including a cell area having a first active region and a peripheral circuit area having a second active region, a direct contact contacting the first active region in the cell area, a bit line structure disposed on the direct contact, a capacitor structure electrically connected to the first active region, a gate structure disposed on the second active region in the peripheral circuit area, lower wiring layers disposed adjacent to the gate structure and electrically connected to the second active region, upper wiring layers disposed on the lower wiring layers, a wiring insulating layer disposed between the lower wiring layers and the upper wiring layers, and upper contact plugs connected to at least one of the lower wiring layers and the upper wiring layers and extending through the wiring insulating layer.