公开(公告)号：US11251188B2

公开(公告)日：2022-02-15

申请号：US16990305

申请日：2020-08-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seok-Hyun Kim ,  Joon Young Kang ,  Youngjun Kim ,  Jinhyung Park ,  Ho-Ju Song ,  Sang-Jun Lee ,  Hyeran Lee ,  Bong-Soo Kim ,  Sungwoo Kim

IPC: H01L27/088 ,  H01L21/00 ,  H01L27/108

Abstract: A semiconductor memory device including: a substrate including a cell array region and a boundary region; a first recess region at an upper portion of the substrate in the cell array region; a first bit line extending onto the boundary region and crossing the first recess region; a bit line contact in the first recess region and contacting the first bit line; a second bit line spaced apart from the first recess region and adjacent to the first bit line, the second bit line crossing the cell array region and the boundary region; a cell buried insulation pattern between a side surface of the first bit line contact and an inner wall of the first recess region; and a boundary buried insulation pattern covering sidewalls of the first bit line and the second bit line in the boundary region and including a same material as the cell buried insulation pattern.

公开(公告)号：US20210035983A1

公开(公告)日：2021-02-04

申请号：US16826655

申请日：2020-03-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hoju Song ,  Seokhyun Kim ,  Youngjun Kim ,  Jinhyung Park ,  Hyeran Lee ,  Bongsoo Kim ,  Sungwoo Kim

IPC: H01L27/108

Abstract: A method of manufacturing a semiconductor memory device includes forming bit line structures extending in a first horizontal direction on a substrate, and insulating spacer structures covering opposite sidewalls of each bit line structure, forming a preliminary buried contact material layer and a mold layer to respectively fill lower and upper portions of a space between a pair of insulating spacer structures, patterning the mold layer and the preliminary buried contact material layer into mold patterns spaced apart from each other in a second horizontal direction and buried contacts spaced apart from each other in the second horizontal direction, forming insulating fences among the mold patterns separated from each other and among the buried contacts separated from each other, removing the mold patterns to expose the buried contacts, and forming landing pads on the exposed buried contacts, each landing pad connected to a corresponding one of the exposed buried contacts.

公开(公告)号：US10446560B2

公开(公告)日：2019-10-15

申请号：US15986064

申请日：2018-05-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sungwoo Kim ,  Bong-Soo Kim ,  Youngbae Kim ,  Kijae Hur ,  Gwanhyeob Koh ,  Hyeongsun Hong ,  Yoosang Hwang

IPC: H01L27/00 ,  H01L27/108 ,  H01L27/24 ,  H01L27/22

Abstract: A semiconductor device including: a first memory section, a first peripheral circuit section, and a second peripheral circuit section on a substrate; a second memory section on the second peripheral circuit section; and a wiring section between the second peripheral circuit section and the second memory section, the first memory section includes a plurality of first memory cells, the first memory cells each including a cell transistor and a capacitor connected to the cell transistor, the second memory section includes a plurality of second memory cells, the second memory cells each including a variable resistance element and a select element in series, and the wiring section includes a plurality of line patterns, at least one of the line patterns and at least one of the capacitors at the same level from the substrate, the second memory cells are higher from the substrate than the at least one of the capacitors.

公开(公告)号：US10395706B2

公开(公告)日：2019-08-27

申请号：US15984914

申请日：2018-05-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sungwoo Kim ,  Bong-Soo Kim ,  Youngbae Kim ,  Kijae Hur ,  Gwanhyeob Koh ,  Hyeongsun Hong ,  Yoosang Hwang

IPC: H01L27/00 ,  G11C11/00 ,  H01L23/528 ,  H01L27/108 ,  H01L27/24 ,  H01L49/02 ,  H01L45/00

Abstract: A semiconductor device including: a first memory section, a first peripheral circuit section, and a second peripheral circuit section that are disposed next to each other on a substrate; and a second memory section laterally spaced apart from the first memory section, the second peripheral circuit section and the second memory section disposed next to each other on the substrate, wherein the first memory section includes a plurality of first memory cells, each of the first memory cells including a cell transistor and a capacitor connected to the cell transistor, and the second memory section includes a plurality of second memory cells, each of the second memory cells including a variable resistance element and a select element coupled in series to each other, wherein the second memory cells are higher from the substrate than each of the capacitors.