公开(公告)号：US10784864B1

公开(公告)日：2020-09-22

申请号：US16533738

申请日：2019-08-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Matthew Berzins ,  Lalitkumar Motagi ,  Shyam Agarwal

IPC: H03K19/00 ,  G06F1/3237 ,  H03C3/09 ,  G06F1/08

Abstract: According to one general aspect, an apparatus may include a latch circuit configured to, depending in part upon a state or at least one enable signal, pass a clock signal to an output signal. The latch circuit may include an input stage controlled by the clock signal and the enable signal(s). The latch may include an output stage configured to produce the output signal. The input and output stages may share a common transistor controlled by the clock signal.

公开(公告)号：US10784198B2

公开(公告)日：2020-09-22

申请号：US15681243

申请日：2017-08-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Rwik Sengupta ,  Andrew Paul Hoover ,  Matthew Berzins ,  Sam Tower ,  Mark S. Rodder

IPC: H01L23/528 ,  H01L27/02 ,  H01L23/522 ,  H01L21/3213 ,  H01L21/311 ,  H01L21/768 ,  H01L21/321 ,  H01L23/532 ,  H01L27/118

Abstract: A semiconductor integrated circuit including a substrate, a series of metal layers, and a series of insulating layers. The metal layers and the insulating layers are alternately arranged in a stack on the substrate. The semiconductor integrated circuit also includes at least two standard cells in the substrate and at least one power rail crossing over boundaries of the at least two standard cells. The power rail includes a vertical section of conductive material extending continuously through at least two vertical levels of the stack. The two vertical levels of the stack include one metal layer and one insulating layer. The insulating layer is above the metal layer.

公开(公告)号：US10382017B1

公开(公告)日：2019-08-13

申请号：US16151338

申请日：2018-10-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Matthew Berzins ,  Sumanth Suraneni

IPC: H03K3/356

Abstract: Inventive aspects include a dynamic flip flop, comprising a data independent P-stack feedback circuit. The data independent P-stack feedback circuit may include a first P-type transistor gated by a first dynamic inverted net signal, and a second P-type transistor gated by an inverted clock signal. A drain of the second P-type transistor may be coupled to a source of the first P-type transistor. A source of the second P-type transistor may be coupled to a node that is configured to receive a second dynamic inverted net signal. The source of the second P-type transistor may be directly coupled to the node that is configured to receive the second dynamic inverted net signal instead of a constant power source. The data independent P-stack feedback circuit may include one or more delay stages to eliminate race conditions.

公开(公告)号：US10298235B2

公开(公告)日：2019-05-21

申请号：US15629729

申请日：2017-06-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： James Jung Lim ,  Matthew Berzins

IPC: H03K3/356 ,  H03K19/00 ,  H03K23/58

Abstract: Embodiments include an integrated clock gating (ICG) cell. The low power ICG cell may include an input condition determination circuit configured to generate a temporary inverted clock signal and an inverted output signal. The low power ICG cell may include an enable control logic circuit configured to receive the temporary inverted clock signal and the inverted output signal from the input condition determination circuit. The low power ICG cell may include a latch circuit coupled to the enable control logic circuit and configured to latch an input value dependent on at least the inverted output signal and the temporary inverted clock signal. The input condition determination circuit is configured to generate the temporary inverted clock signal only when it is needed.

公开(公告)号：US20180269152A1

公开(公告)日：2018-09-20

申请号：US15681243

申请日：2017-08-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Rwik Sengupta ,  Andrew Paul Hoover ,  Matthew Berzins ,  Sam Tower ,  Mark S. Rodder

IPC: H01L23/528 ,  H01L27/02 ,  H01L23/522 ,  H01L21/3213 ,  H01L21/311 ,  H01L21/768 ,  H01L21/321

Abstract: A semiconductor integrated circuit including a substrate, a series of metal layers, and a series of insulating layers. The metal layers and the insulating layers are alternately arranged in a stack on the substrate. The semiconductor integrated circuit also includes at least two standard cells in the substrate and at least one power rail crossing over boundaries of the at least two standard cells. The power rail includes a vertical section of conductive material extending continuously through at least two vertical levels of the stack. The two vertical levels of the stack include one metal layer and one insulating layer. The insulating layer is above the metal layer.