公开(公告)号：US10298235B2

公开(公告)日：2019-05-21

申请号：US15629729

申请日：2017-06-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： James Jung Lim ,  Matthew Berzins

IPC: H03K3/356 ,  H03K19/00 ,  H03K23/58

Abstract: Embodiments include an integrated clock gating (ICG) cell. The low power ICG cell may include an input condition determination circuit configured to generate a temporary inverted clock signal and an inverted output signal. The low power ICG cell may include an enable control logic circuit configured to receive the temporary inverted clock signal and the inverted output signal from the input condition determination circuit. The low power ICG cell may include a latch circuit coupled to the enable control logic circuit and configured to latch an input value dependent on at least the inverted output signal and the temporary inverted clock signal. The input condition determination circuit is configured to generate the temporary inverted clock signal only when it is needed.