公开(公告)号：US20250079424A1

公开(公告)日：2025-03-06

申请号：US18757933

申请日：2024-06-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunsoo Chung ,  Kwangsoo Kim ,  Chiwoo Lee

IPC: H01L25/16 ,  G02B6/42 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48

Abstract: A semiconductor package includes a redistribution layer, a photonic integrated circuit (PIC) chip on the redistribution layer, a buffer chip on the redistribution layer, an electronic integrated circuit (EIC) chip on the PIC chip and the buffer chip, and a plurality of stacked structures on the buffer chip, each of the plurality of stacked structures including a plurality of stacked semiconductor chips. The plurality of stacked structures are spaced apart from one another in a horizontal direction, and a portion of the EIC chip overlaps the PIC chip in a vertical direction, and another portion of the EIC chip overlaps the buffer chip in a vertical direction.

公开(公告)号：US20250046749A1

公开(公告)日：2025-02-06

申请号：US18783805

申请日：2024-07-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunsoo Chung ,  Kwangsoo Kim ,  Inhyo Hwang

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L25/18 ,  H10B80/00

Abstract: A semiconductor package includes an interposer; a plurality of semiconductor devices that are on the interposer and spaced apart from each other; and a package underfill layer that includes a first underfill layer in a first gap that is between the plurality of semiconductor devices and a second underfill layer in a second gap that is between the plurality of semiconductor devices and the interposer, where the second underfill layer includes a second underfill layer side surface that faces a lateral direction, where the second underfill layer side surface does not contact the plurality of semiconductor devices and a portion of the interposer that is adjacent to the second gap, where the second underfill layer side surface extends between a top surface of the interposer and bottom surfaces of the plurality of semiconductor devices and extends from a lower outer boundary.

公开(公告)号：US20240412350A1

公开(公告)日：2024-12-12

申请号：US18406546

申请日：2024-01-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minsu Jo ,  Hankyoul Moon ,  Gawoon Bang ,  Woohyeon So ,  Jongsun An ,  Jooyoun Kang ,  Kwangsoo Kim ,  Karam Lee ,  Kwangsung Lee ,  Sewon Jeon

IPC: G06T7/00 ,  G06T5/50 ,  G06T5/60 ,  G06T5/80 ,  G06T7/586 ,  G06V10/143 ,  G06V10/60 ,  G06V10/77 ,  G06V10/82

Abstract: An optical metrology device includes a lighting unit configured to simultaneously illuminate first illumination light at a first angle of incidence having a difference more than a critical angle from a measurement angle, and second illumination light having a wavelength, different from a wavelength of the first illumination light, at a second angle of incidence having a difference of equal to or less than the critical angle from the measurement angle, onto a surface of a substrate; an optical system configured to collect reflected light from the surface of the substrate according to the first illumination light and the second illumination light; and a multichannel camera configured to generate an original image in which a dark field image and a bright field image of the surface of the substrate are integrated, based on the reflected light collected by the optical system.

公开(公告)号：US11387184B2

公开(公告)日：2022-07-12

申请号：US16885933

申请日：2020-05-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junhyoung Kim ,  Joongshik Shin ,  Kwangsoo Kim

IPC: H01L23/535 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/1157 ,  H01L27/11582 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11573

Abstract: A three-dimensional semiconductor device may include a substrate having a cell area and an extension area, a word line stack disposed above the substrate, the word line stack including mold layers and word lines alternately stacked, vertical channel structures vertically penetrating the word line stack in the cell area, and a first extension through-via structure vertically penetrating the word line stack in the extension area. The first extension through-via structure may include a first via plug and a first via liner layer surrounding sidewalls of the first via plug. The first via liner layer may include first dents respectively disposed at the same levels horizontally as the word lines of the word line stack.