公开(公告)号：US20230230943A1

公开(公告)日：2023-07-20

申请号：US18125989

申请日：2023-03-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yongkoon Lee ,  Jingu Kim ,  SANGKYU LEE ,  Seokkyu Choi

IPC: H01L23/66 ,  H01L23/538 ,  H01L23/00 ,  H01L21/683 ,  H01L21/48 ,  H01L21/56 ,  H01Q9/04 ,  H01Q19/00 ,  H01L23/31

CPC classification number: H01L23/66 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/20 ,  H01L21/6835 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/565 ,  H01L21/568 ,  H01L24/19 ,  H01Q9/0407 ,  H01Q19/005 ,  H01L23/3121 ,  H01L2221/68372 ,  H01L2223/6677 ,  H01L2224/214

Abstract: A semiconductor package includes a supporting wiring structure including a first redistribution dielectric layer and a first redistribution conductive structure; a frame on the supporting wiring structure, having a mounting space and a through hole, and including a conductive material; a semiconductor chip in the mounting space and electrically connected to the first redistribution conductive structure; a cover wiring structure on the frame and the semiconductor chip and including a second redistribution dielectric layer and a second redistribution conductive structure; an antenna structure on the cover wiring structure; a connection structure extending in the through hole and electrically connecting the first redistribution conductive structure to the second redistribution conductive structure; and a dielectric filling member between the connection structure in the through hole and the frame and surrounding the semiconductor chip, the frame, and the connection structure.

公开(公告)号：US20220102309A1

公开(公告)日：2022-03-31

申请号：US17337250

申请日：2021-06-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangkyu Lee ,  Jingu Kim ,  Yongkoon Lee

IPC: H01L23/00 ,  H01L23/31

Abstract: A semiconductor package includes a support member, a semiconductor chip arranged in the support member such that a front surface and a backside surface of the semiconductor chip are exposed from a second surface of the support member and a first surface opposite to the second surface respectively, a lower redistribution wiring layer covering the second surface of the support member and including first redistribution wirings electrically connected to chip pads provided at the front surface of the semiconductor chip and vertical connection structures of the support member respectively, and an upper redistribution wiring layer covering the first surface of the support substrate, and including second redistribution wirings electrically connected to the vertical connection structures and a thermal pattern provided on the exposed backside surface of the semiconductor chip.

公开(公告)号：US20220102236A1

公开(公告)日：2022-03-31

申请号：US17235502

申请日：2021-04-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jingu Kim ,  Sangkyu Lee ,  Yongkoon Lee ,  Seokkyu Choi

IPC: H01L23/367 ,  H01L23/31 ,  H01L23/538 ,  H01L23/00 ,  H01L25/10

Abstract: A semiconductor package includes a connection layer, a semiconductor chip disposed at a center portion of the connection layer, an adhesive layer disposed on the semiconductor chip, a heat spreader layer disposed on the adhesive layer, and a lower redistribution layer disposed on the connection layer and a bottom surface of the semiconductor chip. A width of the adhesive layer is the same as a width of the semiconductor chip, and a width of the heat spreader layer is less than the width of the adhesive layer.

公开(公告)号：US20240258276A1

公开(公告)日：2024-08-01

申请号：US18446844

申请日：2023-08-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wooyoung Kim ,  Sangkyu Lee ,  Jingu Kim

IPC: H01L25/065 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L23/498 ,  H01L25/10

CPC classification number: H01L25/0657 ,  H01L21/56 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/05 ,  H01L24/08 ,  H01L24/16 ,  H01L24/80 ,  H01L24/81 ,  H01L25/105 ,  H01L2224/05647 ,  H01L2224/08145 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/80379 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/81

Abstract: A semiconductor package may include: a front side redistribution layer; a three-dimensional integrated circuit (3D IC) structure on the front side redistribution layer, the 3D IC structure including a first semiconductor chip die and a second semiconductor chip die having through-silicon vias (TSVs), the first semiconductor chip die on the second semiconductor chip die and electrically coupled with the front side redistribution layer by the TSVs; a printed circuit board on the front side redistribution layer and surrounding the 3D IC structure; a molding material on the front side redistribution layer and at least partially encapsulating the 3D IC structure and the printed circuit board; and a back side redistribution layer on the molding material.

公开(公告)号：US12040248B2

公开(公告)日：2024-07-16

申请号：US18099663

申请日：2023-01-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jingu Kim ,  Sangkyu Lee ,  Yongkoon Lee ,  Seokkyu Choi

IPC: H01L23/367 ,  H01L23/00 ,  H01L23/31 ,  H01L23/538 ,  H01L25/10

CPC classification number: H01L23/367 ,  H01L23/3128 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/20 ,  H01L25/105 ,  H01L2224/214 ,  H01L2225/1035 ,  H01L2225/1052 ,  H01L2225/1058 ,  H01L2225/1094

Abstract: A semiconductor package includes a connection layer, a semiconductor chip disposed at a center portion of the connection layer, an adhesive layer disposed on the semiconductor chip, a heat spreader layer disposed on the adhesive layer, and a lower redistribution layer disposed on the connection layer and a bottom surface of the semiconductor chip. A width of the adhesive layer is the same as a width of the semiconductor chip, and a width of the heat spreader layer is less than the width of the adhesive layer.

公开(公告)号：US11942434B2

公开(公告)日：2024-03-26

申请号：US17731841

申请日：2022-04-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sangkyu Lee ,  Jingu Kim ,  Kyungdon Mun ,  Shanghoon Seo ,  Jeongho Lee

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L23/00 ,  H01L23/31 ,  H01L25/00 ,  H01L25/10

CPC classification number: H01L23/5389 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/562 ,  H01L24/19 ,  H01L24/20 ,  H01L25/105 ,  H01L25/50 ,  H01L2221/68372 ,  H01L2224/214 ,  H01L2225/1035 ,  H01L2225/1052 ,  H01L2225/1058 ,  H01L2924/3511

Abstract: A semiconductor package is disclosed. The semiconductor package includes a back-side wiring substrate and a front-side redistribution layer which are in parallel, and a connector, a semiconductor chip and an encapsulator which are between the back-side wiring substrate and the front-side redistribution layer. The encapsulator surrounds surfaces of the connector and the semiconductor chip. The back-side wiring substrate includes a core layer, a back-side via plug extending through the core layer, and a back-side redistribution layer on the back-side via plug.

公开(公告)号：US20230352432A1

公开(公告)日：2023-11-02

申请号：US18218909

申请日：2023-07-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangkyu Lee ,  Jingu Kim ,  Yongkoon Lee

IPC: H01L23/00 ,  H01L23/31

CPC classification number: H01L24/20 ,  H01L23/3121 ,  H01L24/08 ,  H01L2224/221 ,  H01L2224/081 ,  H01L2224/48227 ,  H01L24/13 ,  H01L25/0657

Abstract: A semiconductor package includes a support member, a semiconductor chip arranged in the support member such that a front surface and a backside surface of the semiconductor chip are exposed from a second surface of the support member and a first surface opposite to the second surface respectively, a lower redistribution wiring layer covering the second surface of the support member and including first redistribution wirings electrically connected to chip pads provided at the front surface of the semiconductor chip and vertical connection structures of the support member respectively, and an upper redistribution wiring layer covering the first surface of the support substrate, and including second redistribution wirings electrically connected to the vertical connection structures and a thermal pattern provided on the exposed backside surface of the semiconductor chip.

公开(公告)号：US11735553B2

公开(公告)日：2023-08-22

申请号：US17337250

申请日：2021-06-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangkyu Lee ,  Jingu Kim ,  Yongkoon Lee

IPC: H01L23/00 ,  H01L23/31 ,  H01L25/065

CPC classification number: H01L24/20 ,  H01L23/3121 ,  H01L24/08 ,  H01L24/13 ,  H01L24/48 ,  H01L25/0657 ,  H01L2224/081 ,  H01L2224/13024 ,  H01L2224/221 ,  H01L2224/48227 ,  H01L2225/0651

Abstract: A semiconductor package includes a support member, a semiconductor chip arranged in the support member such that a front surface and a backside surface of the semiconductor chip are exposed from a second surface of the support member and a first surface opposite to the second surface respectively, a lower redistribution wiring layer covering the second surface of the support member and including first redistribution wirings electrically connected to chip pads provided at the front surface of the semiconductor chip and vertical connection structures of the support member respectively, and an upper redistribution wiring layer covering the first surface of the support substrate, and including second redistribution wirings electrically connected to the vertical connection structures and a thermal pattern provided on the exposed backside surface of the semiconductor chip.

公开(公告)号：US20230223353A1

公开(公告)日：2023-07-13

申请号：US17976775

申请日：2022-10-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jingu Kim ,  Taesung Jeong ,  Doohwan Lee

IPC: H01L23/552 ,  H01L23/498 ,  H01L23/31 ,  H01L25/10 ,  H01L23/538

CPC classification number: H01L23/552 ,  H01L23/3121 ,  H01L23/5385 ,  H01L23/49811 ,  H01L23/49822 ,  H01L25/105 ,  H01L24/16 ,  H01L2224/16227

Abstract: A semiconductor package includes: a first redistribution layer including a first wiring; a die located on the first redistribution layer; and a shielding structure surrounding the die from an upper surface and side surfaces of the die, wherein the shielding structure includes: a shielding wall that is spaced apart from the side surfaces of the die and surrounds the side surfaces of the die; and a shielding cover that is spaced apart from the upper surface of the die and surrounds the upper surface of the die.

公开(公告)号：US12154873B2

公开(公告)日：2024-11-26

申请号：US18125989

申请日：2023-03-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yongkoon Lee ,  Jingu Kim ,  Sangkyu Lee ,  Seokkyu Choi

IPC: H01L23/66 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L23/00 ,  H01L23/31 ,  H01L23/538 ,  H01Q9/04 ,  H01Q19/00

Abstract: A semiconductor package includes a supporting wiring structure including a first redistribution dielectric layer and a first redistribution conductive structure; a frame on the supporting wiring structure, having a mounting space and a through hole, and including a conductive material; a semiconductor chip in the mounting space and electrically connected to the first redistribution conductive structure; a cover wiring structure on the frame and the semiconductor chip and including a second redistribution dielectric layer and a second redistribution conductive structure; an antenna structure on the cover wiring structure; a connection structure extending in the through hole and electrically connecting the first redistribution conductive structure to the second redistribution conductive structure; and a dielectric filling member between the connection structure in the through hole and the frame and surrounding the semiconductor chip, the frame, and the connection structure.