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    NONVOLATILE MEMORY DEVICES WITH ALIGNED TRENCH ISOLATION REGIONS
    11.
    发明申请
    NONVOLATILE MEMORY DEVICES WITH ALIGNED TRENCH ISOLATION REGIONS 有权
    具有对准的TRENCH隔离区域的非易失性存储器件

    公开(公告)号：US20140197465A1

    公开(公告)日：2014-07-17

    申请号：US14136273

    申请日：2013-12-20

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Joon-Young Choi ,  Sang-Eun Lee ,  Sam-Jong Choi ,  Jin-Ho Kim

    IPC: H01L29/04 ,  H01L29/792 ,  H01L29/788

    CPC classification number: H01L29/045 ,  H01L27/1157 ,  H01L29/7881 ,  H01L29/792

    Abstract: A nonvolatile memory device includes a substrate, an elongate isolation region including a field insulation film disposed in a trench in the substrate, and a word line crossing the insulation region and including a tunneling insulation layer on an active region of the substrate adjacent the isolation region, a charge storage layer on the tunneling insulation layer and a blocking insulation layer on the charge storage layer. A first plane index of a bottom surface of the trench has a first interface trap density and a second plane index of a sidewall of the trench has a second interface trap density equal to or less than the first interface trap density. In some embodiments, the first plane index may be (100) and the second plane index may be (100) or (310).

    Abstract translation: 非易失性存储器件包括衬底，包括设置在衬底中的沟槽中的场绝缘膜的细长隔离区域和与绝缘区域交叉的字线，并且在邻近隔离区域的衬底的有源区域上包括隧道绝缘层 ，隧道绝缘层上的电荷存储层和电荷存储层上的阻挡绝缘层。 沟槽的底表面的第一平面折射率具有第一界面陷阱密度，并且沟槽的侧壁的第二平面折射率具有等于或小于第一界面陷阱密度的第二界面陷阱密度。 在一些实施例中，第一平面索引可以是（100），第二平面索引可以是（100）或（310）。

    Nonvolatile memory devices with aligned trench isolation regions
    14.
    发明授权
    Nonvolatile memory devices with aligned trench isolation regions 有权
    具有对准沟槽隔离区域的非易失性存储器件

    公开(公告)号：US09190464B2

    公开(公告)日：2015-11-17

    申请号：US14136273

    申请日：2013-12-20

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Joon-Young Choi ,  Sang-Eun Lee ,  Sam-Jong Choi ,  Jin-Ho Kim

    IPC: H01L29/04 ,  H01L29/788 ,  H01L29/792 ,  H01L27/115

    CPC classification number: H01L29/045 ,  H01L27/1157 ,  H01L29/7881 ,  H01L29/792

    Abstract: A nonvolatile memory device includes a substrate, an elongate isolation region including a field insulation film disposed in a trench in the substrate, and a word line crossing the insulation region and including a tunneling insulation layer on an active region of the substrate adjacent the isolation region, a charge storage layer on the tunneling insulation layer and a blocking insulation layer on the charge storage layer. A first plane index of a bottom surface of the trench has a first interface trap density and a second plane index of a sidewall of the trench has a second interface trap density equal to or less than the first interface trap density. In some embodiments, the first plane index may be (100) and the second plane index may be (100) or (310).

    Abstract translation: 非易失性存储器件包括衬底，包括设置在衬底中的沟槽中的场绝缘膜的细长隔离区域和与绝缘区域交叉的字线，并且在邻近隔离区域的衬底的有源区域上包括隧道绝缘层 ，隧道绝缘层上的电荷存储层和电荷存储层上的阻挡绝缘层。 沟槽的底表面的第一平面折射率具有第一界面陷阱密度，并且沟槽的侧壁的第二平面折射率具有等于或小于第一界面陷阱密度的第二界面陷阱密度。 在一些实施例中，第一平面索引可以是（100），第二平面索引可以是（100）或（310）。

    Substrate carrier
    16.
    发明授权
    Substrate carrier 有权

    公开(公告)号：US10790176B2

    公开(公告)日：2020-09-29

    申请号：US16012045

    申请日：2018-06-19

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Du-Sik Bae ,  Hang-Ryong Lim ,  Se-Won Ko ,  Yoon-Mi Lee ,  Jin-Ho Kim ,  Jung-Dae Park ,  Min-Seon Lee ,  Yeong-Cheol Lee

    IPC: H01L21/67 ,  H01L21/673

    Abstract: A substrate carrier may include a carrier body and a first sensor unit. The carrier body may include an internal space, an inlet port and an outlet port. The internal space may be configured to receive a substrate. A purge gas may be introduced into the internal space through the inlet port. A gas in the internal space may be exhausted through the outlet port. The first sensor unit may be at the outlet port and configured to detect environmental properties of the internal space in real time. Thus, a generation or cause of a contaminant in the carrier body may be accurately identified.

    METHOD OF OPERATING ACCELERATION SENSOR AND ELECTRONIC DEVICE THEREOF
    19.
    发明申请
    METHOD OF OPERATING ACCELERATION SENSOR AND ELECTRONIC DEVICE THEREOF 审中-公开
    操作加速传感器及其电子设备的方法

    公开(公告)号：US20150112633A1

    公开(公告)日：2015-04-23

    申请号：US14521312

    申请日：2014-10-22

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jae-Hyeok Lee ,  Jin-Ho Kim

    IPC: G01P1/12 ,  G01P15/00

    CPC classification number: G01P1/127 ,  G01P13/00

    Abstract: Provided is an acceleration sensor operating method of an electronic device. The method includes checking whether at least one movement generation means operates. The method also includes changing a sampling frequency of the acceleration sensor when the movement generation means operates. The method further includes receiving a sensor value of the acceleration sensor according to the changed sampling frequency.

    Abstract translation: 提供一种电子设备的加速度传感器操作方法。 该方法包括检查至少一个移动发生装置是否运行。 该方法还包括当移动产生装置操作时改变加速度传感器的采样频率。 该方法还包括根据改变的采样频率接收加速度传感器的传感器值。

    THREE-DIMENSIONAL MICROELECTRONIC DEVICES INCLUDING HORIZONTAL AND VERTICAL PATTERNS
    20.
    发明申请
    THREE-DIMENSIONAL MICROELECTRONIC DEVICES INCLUDING HORIZONTAL AND VERTICAL PATTERNS 有权
    包括水平和垂直图案的三维微电子器件

    公开(公告)号：US20130256775A1

    公开(公告)日：2013-10-03

    申请号：US13901205

    申请日：2013-05-23

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sun-il Shim ,  Sung-Hoi Hur ,  Jin-Ho Kim ,  Su-Youn Yi

    IPC: H01L27/115

    CPC classification number: H01L27/1158 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11568 ,  H01L27/11578 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7881 ,  H01L29/792 ,  H01L29/7926

    Abstract: A vertical NAND flash memory device includes a substrate having a face and a string of serially connected flash memory cells on the substrate. A first flash memory cell is adjacent the face, and a last flash memory cell is remote from the face. The flash memory cells include repeating layer patterns that are stacked on the face, and a pillar that extends through the series of repeating layer patterns. The pillar includes at least one oblique wall. At least two of the series of repeating layer patterns in the string are of different thicknesses. Other vertical microelectronic devices and related fabrication methods are also described.

    Abstract translation: 垂直NAND闪速存储器件包括在衬底上具有面和串联的闪存单元串的衬底。 第一闪存单元与面相邻，并且最后的闪存单元远离面。 闪存单元包括堆叠在表面上的重复层图案和延伸穿过一系列重复层图案的柱。 支柱包括至少一个斜壁。 串中重复层图案的系列中的至少两个具有不同的厚度。 还描述了其它垂直微电子器件和相关的制造方法。

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