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    METHOD OF OPERATING A SYSTEM INCLUDING A PARAMETER MONITORING CIRCUIT
    11.
    发明申请
    METHOD OF OPERATING A SYSTEM INCLUDING A PARAMETER MONITORING CIRCUIT 有权

    公开(公告)号：US20210226613A1

    公开(公告)日：2021-07-22

    申请号：US17222033

    申请日：2021-04-05

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Dongho SHIN ,  Kyungtae KANG ,  Junha LEE ,  Tongsung KIM ,  Jangwoo LEE ,  Jeongdon IHM ,  Byunghoon JEONG

    IPC: H03K3/017 ,  H03K19/21 ,  H03K5/24

    Abstract: A method of operating a system including a parameter monitoring circuit and a host, includes generating a first parameter applying a first code to a current parameter, wherein a first offset is applied to the first code; generating a first comparison result by comparing the first parameter with a reference parameter value; generating a second parameter applying a second code to the current parameter, wherein a second offset is applied to the second code; generating a second comparison result by comparing the second parameter with the reference parameter value; detecting an error in the current parameter, based on the first comparison result and the second comparison result; and providing a signal based on the error to the host.

    MULTI-CHIP PACKAGE WITH REDUCED CALIBRATION TIME AND ZQ CALIBRATION METHOD THEREOF
    13.
    发明申请
    MULTI-CHIP PACKAGE WITH REDUCED CALIBRATION TIME AND ZQ CALIBRATION METHOD THEREOF 有权

    公开(公告)号：US20210065753A1

    公开(公告)日：2021-03-04

    申请号：US17012845

    申请日：2020-09-04

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Junha LEE ,  Seonkyoo LEE ,  Jeongdon IHM ,  Byunghoon JEONG

    IPC: G11C7/10 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00

    Abstract: A multi-chip package with reduced calibration time and an impedance control (ZQ) calibration method thereof are provided. A master chip of the multi-chip package performs a first ZQ calibration operation by using a ZQ resistor, and then, the other slave chips simultaneously perform second ZQ calibration operations with respect to data input/output (DQ) pads of the slave chips by using a termination resistance value of a DQ pad of the master chip on the basis of a one-to-one correspondence relationship with the DQ pad of the master chip. The multi-chip package completes ZQ calibration by performing two ZQ calibration operations, thereby decreasing a ZQ calibration time.

    INTEGRATED CIRCUIT AND STORAGE DEVICE INCLUDING INTEGRATED CIRCUIT
    14.
    发明申请
    INTEGRATED CIRCUIT AND STORAGE DEVICE INCLUDING INTEGRATED CIRCUIT 有权
    集成电路和存储设备，包括集成电路

    公开(公告)号：US20160216319A1

    公开(公告)日：2016-07-28

    申请号：US14957987

    申请日：2015-12-03

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Daehoon NA ,  ChaeHoon KIM ,  HyunJin KIM ,  Jangwoo LEE ,  Jeongdon IHM

    IPC: G01R31/28 ,  G01R31/3177

    CPC classification number: G01R31/31716 ,  G01R31/2884 ,  G01R31/3177

    Abstract: An integrated circuit including first pads and second pads, a first receiver circuit and a first driver circuit respectively connected to the first pad, a second receiver circuit and a second driver circuit respectively connected to the second pad, and a first loopback circuit having a first input terminal electrically connected to the first receiver circuit, a first output terminal electrically connected to the first driver circuit, a second output terminal electrically connected to the second driver circuit, and a second input terminal electrically connected to the second receiver circuit may be provided. At a normal mode, the first loopback circuit electrically connects the first input terminal to the second output terminal and electrically connects the second input terminal to the first output terminal. At a test mode, the first loopback circuit electrically connects the first input terminal to the first output terminal.

    Abstract translation: 包括第一焊盘和第二焊盘的集成电路，分别连接到第一焊盘的第一接收器电路和第一驱动器电路，分别连接到第二焊盘的第二接收器电路和第二驱动器电路，以及第一回路电路， 电连接到第一接收器电路的输入端子，电连接到第一驱动器电路的第一输出端子，电连接到第二驱动器电路的第二输出端子和电连接到第二接收器电路的第二输入端子。 在正常模式下，第一回路电路将第一输入端子与第二输出端子电连接，并将第二输入端子电连接到第一输出端子。 在测试模式下，第一回路电路将第一输入端子与第一输出端子电连接。

    INTERFACE CIRCUIT, MEMORY DEVICE, STORAGE DEVICE, AND METHOD OF OPERATING THE MEMORY DEVICE
    16.
    发明申请
    INTERFACE CIRCUIT, MEMORY DEVICE, STORAGE DEVICE, AND METHOD OF OPERATING THE MEMORY DEVICE 有权

    公开(公告)号：US20220083237A1

    公开(公告)日：2022-03-17

    申请号：US17536506

    申请日：2021-11-29

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Daehoon NA ,  Jangwoo LEE ,  Jeongdon IHM

    IPC: G06F3/06

    Abstract: An interface circuit of a memory device including a plurality of memory dies including a plurality of registers corresponding to the plurality of memory dies, respectively, the plurality of registers each configured to store command information related to a data operation command, a demultiplexer circuit configured to provide input command information to a selected register from among the plurality of registers according to at least one of a first address or a first chip selection signal, the input command information being received from outside the interface circuit, and a multiplexer circuit configured to receive output command information from the selected register from among the plurality of registers and output the output command information according to at least one of a second address or a second chip selection signal may be provided.

    INTERFACE CIRCUIT, MEMORY DEVICE, STORAGE DEVICE, AND METHOD OF OPERATING THE MEMORY DEVICE
    19.
    发明申请
    INTERFACE CIRCUIT, MEMORY DEVICE, STORAGE DEVICE, AND METHOD OF OPERATING THE MEMORY DEVICE 有权

    公开(公告)号：US20210072902A1

    公开(公告)日：2021-03-11

    申请号：US16861802

    申请日：2020-04-29

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Daehoon NA ,  Jangwoo LEE ,  Jeongdon IHM

    IPC: G06F3/06

    Abstract: An interface circuit of a memory device including a plurality of memory dies including a plurality of registers corresponding to the plurality of memory dies, respectively, the plurality of registers each configured to store command information related to a data operation command, a demultiplexer circuit configured to provide input command information to a selected register from among the plurality of registers according to at least one of a first address or a first chip selection signal, the input command information being received from outside the interface circuit, and a multiplexer circuit configured to receive output command information from the selected register from among the plurality of registers and output the output command information according to at least one of a second address or a second chip selection signal may be provided.

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